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Fri, 15 May 2026 05:26:27 -0700 From: Sumit Gupta To: , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 0/2] cpufreq: CPPC: add autonomous mode boot parameter support Date: Fri, 15 May 2026 17:56:22 +0530 Message-ID: <20260515122624.1920637-1-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F4:EE_|DS7PR12MB6117:EE_ X-MS-Office365-Filtering-Correlation-Id: efae3e97-5dcc-452f-0d67-08deb27d3682 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|82310400026|36860700016|56012099003|18002099003|13003099007|921020|11063799003|3023799003; X-Microsoft-Antispam-Message-Info: rWUeJ1XI5uwzBC7KJyK6a/vGr8K5uA9UFzxz2Vv3l5yavufRQFvDtEf9RevXL8gCEqpeJSXX99qO0brhZvgjB3MwKr729RXlxXAB+YFqnrvcGXBDOhpdraMY2JpikjOGh8u6CYltnkNTu3KClh8mIFJTyu0qgC6Syj4YRsxdiw1LV8Y89qrXKDf8ZCmUKM4Idd1xvZXQpZuG6bELFaZUJzWVVgwVvdg1nAeaQRoOEWjWvTNnKOruNHCFJEIrFdC0SYJQZhAaKMjHoiFgQppp1cEB6d3K+8VzNmTG6KPcgV93nInM6IzInqendNKPM/0zvK1vIN8FyzkTFGFkQsxeY5pisv6Ail9GR48jcv5zoOsXgTs+nYK9qZFBw1febdr36IeZ+IdWLYxjRCBETGBti2Y+S8T2yz1umsc+NPOTMdzYta0awV8bS8+2bmhmHmnKdqEQpq0WsjWo3GYOIvYSL8IEDjax/X5OodWMbZE3Q3J8LFtNV0XRLeDm3asBzH2eDg6gosqRalcUsNnb4Bwn3z2Kez4DpntrFErjCb3p8yKaLaU3ruNP1z3e5LYhrTUSzC/atd3vAI8CjoaZWmyj8xBR7JlNfkSWwGK6ZxPlnKbyhX5Yj5r9UAb0IzPMYhnkjmkH2xjUVulgleCzzlVqEraF9ALg0XgDqEW2MbS0SAmhaK+smMFGUylq/Y63wQf7/mSu/m4Z0dGnayFGa4ixzMHDBWVyxCcfIzAp2/ZxgRDKJZ/BB0wCQlWrfn3HpWWDaUcHnp+8JLX19ieZcMss+4MKSYyaor2KN7TQoY+22+Q= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(82310400026)(36860700016)(56012099003)(18002099003)(13003099007)(921020)(11063799003)(3023799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: GVj66gF9RET/jibH1VskvUfjH0leWStYT05m4+BdNT3eKc4wTzm4y9YbNKmxlrtKyf8SjOPY40Dsjz+Hc0vNhxt3bQ99sX11tmSost0/FJBdsi2DNOGXEQG2wmisgtZu8SvtEUsk9mhy5s8MumV0IynDRpOHIIoETluUemUfZdbUt9VRGPNPMSPzvbMonhoqnTBHcR9OSZQNeBHA0q2M+P9N5auBluxfDYwPcvcSDY/Hhn9i10JWo4y2alpXLzw7I5y0BBHrUVlrBttd4wFDU+S1PX76iMKykbNGUUv18iSo8FKRd+ahZ+ZzRmG2pmHLhwM5J4q7AzGU/oPjkoQBGf7QVP3ACGTEdqDleUOHqZGbcG4ShPsHqE2zvgNgAEjqGNFm7GiHcGzS24d1VZ+Pqs/XbD3LKCyG9KpCDvXIzyhe1C61LyHknwh34Hzrp8Tq X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 May 2026 12:26:38.8092 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: efae3e97-5dcc-452f-0d67-08deb27d3682 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6117 This series adds a kernel boot parameter 'cppc_cpufreq.auto_sel_mode' to enable CPPC autonomous performance selection on all CPUs at system startup, avoiding per-CPU sysfs scripting at every boot. When autonomous mode is enabled, the hardware automatically adjusts CPU performance based on workload demands using Energy Performance Preference (EPP) hints. Patch 1: sets CPPC Enable Register for both OS-driven and autonomous CPPC control modes. It can be applied independently of patch 2. Patch 2: adds the auto_sel_mode boot parameter with two modes: - performance (or 1): override EPP to performance preference (0x0) - default_epp (or 2): preserve EPP value programmed by BIOS/firmware Patch 2 depends on Pierre's series [3] ("cpufreq: Set policy->min and max as real QoS constraints") so that policy->min/max set during cppc_cpufreq_cpu_init() are not overridden by cpufreq_set_policy(). v2[2] -> v3: - Split cppc_set_enable() into a separate patch (1/2). - Change auto_sel_mode to accept EPP mode (string or numeric). - Drop clamp on desired_perf; initialize it to max_perf as a starting hint. - cppc_set_perf() failure during autonomous setup is non-fatal. - cppc_set_auto_sel() failure: fall back to OS-driven mode. - Documentation: list 'performance' and 'default_epp' modes as per code. - Removed Randy Dunlap's reviewed-by from documentation as some change. Sumit Gupta (2): cpufreq: CPPC: Set CPPC Enable register in cpu_init cpufreq: CPPC: add autonomous mode boot parameter support .../admin-guide/kernel-parameters.txt | 16 +++ drivers/cpufreq/cppc_cpufreq.c | 130 +++++++++++++++++- 2 files changed, 141 insertions(+), 5 deletions(-) [1] v1: https://lore.kernel.org/lkml/20260317151053.2361475-1-sumitg@nvidia.com/ [2] v2: https://lore.kernel.org/lkml/20260424201814.230071-1-sumitg@nvidia.com/ [3] https://lore.kernel.org/lkml/20260511135538.522653-1-pierre.gondois@arm.com/ -- 2.34.1