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Sun, 17 May 2026 04:27:18 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Jiri Pirko , Simon Horman , "Jonathan Corbet" , Shuah Khan , "Saeed Mahameed" , Leon Romanovsky , Tariq Toukan , Mark Bloch , Vlad Dumitrescu , Aleksandr Loktionov , Daniel Zahka , "David Ahern" , Nikolay Aleksandrov , , , , , Gal Pressman , Dragos Tatulea , Jiri Pirko , Nikolay Aleksandrov Subject: [PATCH net-next 2/2] net/mlx5: implement max_sfs parameter Date: Sun, 17 May 2026 14:27:00 +0300 Message-ID: <20260517112700.343575-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260517112700.343575-1-tariqt@nvidia.com> References: <20260517112700.343575-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0002256F:EE_|DM4PR12MB6568:EE_ X-MS-Office365-Filtering-Correlation-Id: 710f8d87-4afc-410c-5a61-08deb407488b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|376014|1800799024|7416014|11063799003|22082099003|56012099003|18002099003|3023799003; X-Microsoft-Antispam-Message-Info: 05MT6lMEQAk6StyrL74C7aF3JIEpmtdiBQhJVYLaBYNmzBW7A4LVoqx6c9BQ34yAFUU3g4BF4i16EPSbb07nVFx2P8tNAp8XbgXUfzcCiJVcicnVAmzKXJeAfK4MqIJo9X3Yl6w6cN7xIH28FzYQgpOLcOuznqSQfVyzXQJ2z37p2c2Ri4buzYpZ2KPhdR9BAiIRbh4inGuQ03XMNiLvdC9Pk5koSYoMB7GKedKdw2yd+6gKC+Lkt7JXGzxeFJ7AZMQ98b/hv0NgdGMdYrF8nUxdgvVIA4X5MJWjMAyuC65RcLWTUORBLPEEHGo2xe6oIf/jhbGFuQ73lHcWa23dD/LxeknyfBtFtbfNVYv6Gu4zCnxKrrfxV+XMDwTSu2+Cpf6LmszSix7uJkC6I8fakTe6ljH/Wi4ovtG7S1t8xFLCwEy8Xw9r7lC/x1HU+cR88PBvDByb9ujyJEPI+RhoQlOoHi3XgYqAGtrEMpLKRzodEkxqsGzTCCVSG2ZKBFS1klelOwMR7IfbYJX3OsM+AqQ0Ev8XNQKDdjUl5s/Ycp+bpJNRbury02rfNqEcqWuvf6leUe+LaN8bUtBpNN+EJW8HcPCVhaIWulZzruhJymGELoBZ3bSVPp/mWlbhAJ6V/03R0PLQilsMH/6UFv6i2KxdoAEEoNlPbd0ZNOsiHH+hXlumYzrl4RNjf9y0ggLsa6dQyNTbExmWMThw2hI2KvdoEsc28jX6Nx18p9G4NGY= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(376014)(1800799024)(7416014)(11063799003)(22082099003)(56012099003)(18002099003)(3023799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DlEHwpOVvkuKq2xOSTBGmqTbJM4oFvTznZZlq3aKmUPuTtj4HNwVvY9jUue7RtNEMCscYOzSQ7eUoDxeQaQwnihWObrZyj6JLBXmGZsFKR8aKiSK+HSd4K1XOHSqo8J89GsuR9p2J1yz8CQhsPi4lp/h332s7XODumIvcwST6bViWPS5Jd52jbsFODj+un9c180t7ZHb5Mt6sXn8nvYH3knWC8+QoCpoVwrUPvgemgn9pQE3Shui7QHMfnvHz5WMkocrLO7JxFs5GqdhgCshsqV589s1OrKkVYnnwWa4v9h2iwRVRZ1pZyJVbCU/YlXZj/CdBuMKeJxT3ZYUrfyQYoQjEkYaQdiPRPEYwlY3xmj3quHzimhyxneoOF5hQB4nsxOJyRNa504e36jhi+p0qcI3WGmxWX0rZRcMwPhhlMUTUlHFLlmjd6PKPcAFUdzI X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 May 2026 11:27:30.6139 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 710f8d87-4afc-410c-5a61-08deb407488b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0002256F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6568 From: Nikolay Aleksandrov Implement max_sfs generic parameter to allow users to control the total light-weight NIC subfunctions that can be created using devlink instead of external vendor tools. A value of 0 will effectively disable creation of new subfunction devices. A warning is sent to user-space via extack (returning extack without error code is interpreted as a warning by user-space tools). Signed-off-by: Nikolay Aleksandrov Reviewed-by: David Ahern Signed-off-by: Tariq Toukan --- Documentation/networking/devlink/mlx5.rst | 7 +- .../mellanox/mlx5/core/lib/nv_param.c | 83 ++++++++++++++++++- 2 files changed, 86 insertions(+), 4 deletions(-) diff --git a/Documentation/networking/devlink/mlx5.rst b/Documentation/networking/devlink/mlx5.rst index 4bba4d780a4a..283b93d16861 100644 --- a/Documentation/networking/devlink/mlx5.rst +++ b/Documentation/networking/devlink/mlx5.rst @@ -45,8 +45,13 @@ Parameters - The range is between 1 and a device-specific max. - Applies to each physical function (PF) independently, if the device supports it. Otherwise, it applies symmetrically to all PFs. + * - ``max_sfs`` + - permanent + - The range is between 0 and a device-specific max. + - Applies to each physical function (PF) independently. -Note: permanent parameters such as ``enable_sriov`` and ``total_vfs`` require FW reset to take effect +Note: permanent parameters such as ``enable_sriov``, ``total_vfs` and ``max_sfs`` + require FW reset to take effect .. code-block:: bash diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/nv_param.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/nv_param.c index 19bb620b7436..eff3a67e4ca0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/nv_param.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/nv_param.c @@ -68,7 +68,9 @@ struct mlx5_ifc_mnvda_reg_bits { struct mlx5_ifc_nv_global_pci_conf_bits { u8 sriov_valid[0x1]; - u8 reserved_at_1[0x10]; + u8 reserved_at_1[0xa]; + u8 per_pf_num_sf[0x1]; + u8 reserved_at_c[0x5]; u8 per_pf_total_vf[0x1]; u8 reserved_at_12[0xe]; @@ -93,9 +95,11 @@ struct mlx5_ifc_nv_global_pci_cap_bits { }; struct mlx5_ifc_nv_pf_pci_conf_bits { - u8 reserved_at_0[0x9]; + u8 log_sf_bar_size[0x8]; + u8 pf_total_sf_en[0x1]; u8 pf_total_vf_en[0x1]; - u8 reserved_at_a[0x16]; + u8 reserved_at_a[0x6]; + u8 total_sf[0x10]; u8 reserved_at_20[0x20]; @@ -755,6 +759,76 @@ static int mlx5_devlink_total_vfs_validate(struct devlink *devlink, u32 id, return 0; } +static int mlx5_devlink_max_sfs_get(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx, + struct netlink_ext_ack *extack) +{ + struct mlx5_core_dev *dev = devlink_priv(devlink); + u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] = {}; + void *data; + int err; + + err = mlx5_nv_param_read_per_host_pf_conf(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, "Failed to read PF configuration"); + return err; + } + + data = MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data); + ctx->val.vu32 = MLX5_GET(nv_pf_pci_conf, data, total_sf); + + return 0; +} + +static int mlx5_devlink_max_sfs_set(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx, + struct netlink_ext_ack *extack) +{ + struct mlx5_core_dev *dev = devlink_priv(devlink); + u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] = {}; + void *data; + int err; + + err = mlx5_nv_param_read_global_pci_conf(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to read global PCI configuration"); + return err; + } + + data = MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data); + MLX5_SET(nv_global_pci_conf, data, per_pf_num_sf, !!ctx->val.vu32); + + err = mlx5_nv_param_write(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to change per_pf_num_sf global PCI configuration"); + return err; + } + + memset(mnvda, 0, sizeof(mnvda)); + err = mlx5_nv_param_read_per_host_pf_conf(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, "Failed to read PF configuration"); + return err; + } + + data = MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data); + MLX5_SET(nv_pf_pci_conf, data, log_sf_bar_size, ctx->val.vu32 ? 12 : 0); + MLX5_SET(nv_pf_pci_conf, data, pf_total_sf_en, !!ctx->val.vu32); + MLX5_SET(nv_pf_pci_conf, data, total_sf, ctx->val.vu32); + + err = mlx5_nv_param_write(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to change PF PCI configuration"); + return err; + } + NL_SET_ERR_MSG(extack, "Modifying max_sfs requires a reboot"); + + return 0; +} + static const struct devlink_param mlx5_nv_param_devlink_params[] = { DEVLINK_PARAM_GENERIC(ENABLE_SRIOV, BIT(DEVLINK_PARAM_CMODE_PERMANENT), mlx5_devlink_enable_sriov_get, @@ -763,6 +837,9 @@ static const struct devlink_param mlx5_nv_param_devlink_params[] = { mlx5_devlink_total_vfs_get, mlx5_devlink_total_vfs_set, mlx5_devlink_total_vfs_validate), + DEVLINK_PARAM_GENERIC(MAX_SFS, BIT(DEVLINK_PARAM_CMODE_PERMANENT), + mlx5_devlink_max_sfs_get, + mlx5_devlink_max_sfs_set, NULL), DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_CQE_COMPRESSION_TYPE, "cqe_compress_type", DEVLINK_PARAM_TYPE_STRING, BIT(DEVLINK_PARAM_CMODE_PERMANENT), -- 2.44.0