From: Joel Fernandes <joelagnelf@nvidia.com>
To: linux-kernel@vger.kernel.org
Cc: Miguel Ojeda <ojeda@kernel.org>, Boqun Feng <boqun@kernel.org>,
Gary Guo <gary@garyguo.net>,
Bjorn Roy Baron <bjorn3_gh@protonmail.com>,
Benno Lossin <lossin@kernel.org>,
Andreas Hindborg <a.hindborg@kernel.org>,
Alice Ryhl <aliceryhl@google.com>,
Trevor Gross <tmgross@umich.edu>,
Danilo Krummrich <dakr@kernel.org>,
Dave Airlie <airlied@redhat.com>,
Daniel Almeida <daniel.almeida@collabora.com>,
dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org,
nova-gpu@lists.linux.dev, Nikola Djukic <ndjukic@nvidia.com>,
David Airlie <airlied@gmail.com>,
Boqun Feng <boqun.feng@gmail.com>,
John Hubbard <jhubbard@nvidia.com>,
Alistair Popple <apopple@nvidia.com>,
Timur Tabi <ttabi@nvidia.com>, Edwin Peer <epeer@nvidia.com>,
Alexandre Courbot <acourbot@nvidia.com>,
Andrea Righi <arighi@nvidia.com>,
Andy Ritger <aritger@nvidia.com>, Zhi Wang <zhiw@nvidia.com>,
Balbir Singh <balbirs@nvidia.com>,
Philipp Stanner <phasta@kernel.org>,
alexeyi@nvidia.com, Eliot Courtney <ecourtney@nvidia.com>,
joel@joelfernandes.org, linux-doc@vger.kernel.org,
Joel Fernandes <joelagnelf@nvidia.com>
Subject: [PATCH v1 01/12] rust: pci: add resource_flags accessor
Date: Mon, 18 May 2026 14:03:31 -0400 [thread overview]
Message-ID: <20260518180342.2387845-2-joelagnelf@nvidia.com> (raw)
In-Reply-To: <20260518180342.2387845-1-joelagnelf@nvidia.com>
Add a `Device::resource_flags()` method to the PCI Rust abstraction,
wrapping the C-side static inline `pci_resource_flags()`.
The flags returned correspond to the `IORESOURCE` bitmask carried by a
PCI BAR's `struct resource`.
The immediate motivation is BAR layout discovery on NVIDIA GPUs: a
64-bit BAR consumes two consecutive Linux PCI resource slots (the lower
32 bits at index N and the upper 32 bits at index N+1, with the latter
having no flags or size of its own).
Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com>
---
rust/helpers/pci.c | 6 ++++++
rust/kernel/io/resource.rs | 8 ++++++++
rust/kernel/pci.rs | 14 ++++++++++++++
3 files changed, 28 insertions(+)
diff --git a/rust/helpers/pci.c b/rust/helpers/pci.c
index e44905317d75..51148987618a 100644
--- a/rust/helpers/pci.c
+++ b/rust/helpers/pci.c
@@ -19,6 +19,12 @@ __rust_helper resource_size_t rust_helper_pci_resource_len(struct pci_dev *pdev,
return pci_resource_len(pdev, bar);
}
+__rust_helper unsigned long rust_helper_pci_resource_flags(const struct pci_dev *pdev,
+ int bar)
+{
+ return pci_resource_flags(pdev, bar);
+}
+
__rust_helper bool rust_helper_dev_is_pci(const struct device *dev)
{
return dev_is_pci(dev);
diff --git a/rust/kernel/io/resource.rs b/rust/kernel/io/resource.rs
index b7ac9faf141d..78f353d1605b 100644
--- a/rust/kernel/io/resource.rs
+++ b/rust/kernel/io/resource.rs
@@ -226,10 +226,18 @@ impl Flags {
/// Resource represents a memory region that must be ioremaped using `ioremap_np`.
pub const IORESOURCE_MEM_NONPOSTED: Flags = Flags::new(bindings::IORESOURCE_MEM_NONPOSTED);
+ /// Memory region uses a 64-bit address (consumes two consecutive PCI resource slots).
+ pub const IORESOURCE_MEM_64: Flags = Flags::new(bindings::IORESOURCE_MEM_64);
+
// Always inline to optimize out error path of `build_assert`.
#[inline(always)]
const fn new(value: u32) -> Self {
crate::build_assert!(value as u64 <= c_ulong::MAX as u64);
Flags(value as c_ulong)
}
+
+ /// Wrap a raw `c_ulong` value returned by a C API into [`Flags`].
+ pub(crate) const fn from_raw(value: c_ulong) -> Self {
+ Flags(value)
+ }
}
diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs
index af74ddff6114..d76a1377195e 100644
--- a/rust/kernel/pci.rs
+++ b/rust/kernel/pci.rs
@@ -17,6 +17,7 @@
from_result,
to_result, //
},
+ io::resource,
prelude::*,
str::CStr,
types::Opaque,
@@ -437,6 +438,19 @@ pub fn resource_len(&self, bar: u32) -> Result<bindings::resource_size_t> {
Ok(unsafe { bindings::pci_resource_len(self.as_raw(), bar.try_into()?) })
}
+ /// Returns the resource flags (`IORESOURCE_*`) of the given PCI BAR.
+ pub fn resource_flags(&self, bar: u32) -> Result<resource::Flags> {
+ if !Bar::index_is_valid(bar) {
+ return Err(EINVAL);
+ }
+
+ // SAFETY:
+ // - `bar` is a valid bar number, as guaranteed by the above call to `Bar::index_is_valid`,
+ // - by its type invariant `self.as_raw` is always a valid pointer to a `struct pci_dev`.
+ let raw = unsafe { bindings::pci_resource_flags(self.as_raw(), bar.try_into()?) };
+ Ok(resource::Flags::from_raw(raw))
+ }
+
/// Returns the PCI class as a `Class` struct.
#[inline]
pub fn pci_class(&self) -> Class {
--
2.34.1
next prev parent reply other threads:[~2026-05-18 18:03 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-18 18:03 [PATCH v1 00/12] Introduce nova-core mm prerequisites Joel Fernandes
2026-05-18 18:03 ` Joel Fernandes [this message]
2026-05-18 18:03 ` [PATCH v1 02/12] rust: bitfield: support cast+shift accessor syntax Joel Fernandes
2026-05-18 18:03 ` [PATCH v1 03/12] gpu: nova-core: gsp: Return GspStaticInfo from boot() Joel Fernandes
2026-05-18 18:03 ` [PATCH v1 04/12] gpu: nova-core: gsp: Extract usable FB region from GSP Joel Fernandes
2026-05-18 18:03 ` [PATCH v1 05/12] gpu: nova-core: gsp: Expose total physical VRAM end from FB region info Joel Fernandes
2026-05-18 18:03 ` [PATCH v1 06/12] gpu: nova-core: mm: Add Pfn (Physical Frame Number) type Joel Fernandes
2026-05-18 18:03 ` [PATCH v1 07/12] gpu: nova-core: mm: Add VramAddress type and conversion traits Joel Fernandes
2026-05-18 18:03 ` [PATCH v1 08/12] gpu: nova-core: mm: Add VramAddress arithmetic and ordering Joel Fernandes
2026-05-18 18:03 ` [PATCH v1 09/12] gpu: nova-core: mm: Add support to use PRAMIN windows to write to VRAM Joel Fernandes
2026-05-18 18:03 ` [PATCH v1 10/12] docs: gpu: nova-core: Document the PRAMIN aperture mechanism Joel Fernandes
2026-05-18 18:03 ` [PATCH v1 11/12] gpu: nova-core: mm: Add GpuMm centralized memory manager Joel Fernandes
2026-05-18 18:03 ` [PATCH v1 12/12] gpu: nova-core: mm: Add PRAMIN aperture self-tests Joel Fernandes
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