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Thu, 25 Jun 2026 09:54:44 -0700 From: To: , , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v3 01/11] cxl: Add cxl_get_hdm_info() helper for HDM decoder metadata Date: Thu, 25 Jun 2026 22:23:57 +0530 Message-ID: <20260625165407.1769572-2-mhonap@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260625165407.1769572-1-mhonap@nvidia.com> References: <20260625165407.1769572-1-mhonap@nvidia.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B073:EE_|PH0PR12MB999090:EE_ X-MS-Office365-Filtering-Correlation-Id: 55d9d030-af4e-4bb3-92d1-08ded2da89e4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|82310400026|376014|36860700016|7416014|1800799024|22082099003|18002099003|6133799003|3023799007|56012099006|921020|11063799006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: boB3cjDyAxyvdXhyTa7ivlxL5unlUGeeiMZGazaEYAmdIm+kz3Rr9paX4Q0mw85wZSTmNSgHtU5JMTNJXydiQ5kqesKADdeAS0GdsjCW3qMcz3etGIX8H8yje6TMOgN4Q2rqnwkg2bYXi0NHirbLRaNpm94HVmesPwUrK0bMuZWnamT/BRTkxPLs5xRlCvVB9abDrh6/R7j+gnCtDzGeo0Bw1EWCZa76NUuYLFT+m0irEfCha0U5XaAXCbrJ3vh2gGGzaOOOVIzLGaAARy7oIhMkdyRZqiG+a8BLMmCc2XNLiM7ghqLBLtiDe+k6xj1kuXxN9q+vHIyWwdSeRnSGS2cKMdK/vphL6NnG0Znz1sgnid81ABEgF1fOsJFg7uie/2UnODBDkdWADn3tS8Pz3tfvV+efbWOeKW+B9ijGvzf06OiiGdczA3Bo3W724de4 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jun 2026 16:55:18.9577 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 55d9d030-af4e-4bb3-92d1-08ded2da89e4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B073.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB999090 From: Manish Honap cxl_probe_component_regs() finds the HDM decoder block during device probe and caches its location, but does not record the decoder count and does not expose the result outside drivers/cxl/. In-kernel cxl drivers (Type-2 accelerator drivers, vfio-cxl) need the decoder count and the byte offset and size of the HDM block without re-running the probe sequence. Record decoder_cnt in rmap->count when parsing the HDM capability in cxl_probe_component_regs(), extend struct cxl_reg_map with a count member, and add cxl_get_hdm_info() to return offset, size, and count from the cached map. Export under the CXL namespace. Signed-off-by: Manish Honap --- drivers/cxl/core/pci.c | 33 +++++++++++++++++++++++++++++++++ drivers/cxl/core/regs.c | 1 + include/cxl/cxl.h | 4 ++++ 3 files changed, 38 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 2bcd683aa286..c917608c16f9 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -449,6 +449,39 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, } EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, "CXL"); +/** + * cxl_get_hdm_info - Get HDM decoder register block location and count + * @cxlds: CXL device state (must have component regs enumerated via + * cxl_probe_component_regs()) + * @count: number of HDM decoders (from HDM Capability bits [3:0]) + * @offset: byte offset of HDM decoder block within the component register BAR + * @size: size in bytes of the HDM decoder block + * + * Exported for cxl drivers (in-kernel accelerator drivers, vfio-cxl) that + * need HDM decoder metadata from the cached component-register map without + * re-running the probe sequence. + * + * Return: 0 on success. -ENODEV if the HDM decoder block is not present. + */ +int cxl_get_hdm_info(struct cxl_dev_state *cxlds, u8 *count, + resource_size_t *offset, resource_size_t *size) +{ + struct cxl_reg_map *hdm = &cxlds->reg_map.component_map.hdm_decoder; + + if (WARN_ON(!count || !offset || !size)) + return -EINVAL; + + if (!hdm->valid) + return -ENODEV; + + *count = hdm->count; + *offset = hdm->offset; + *size = hdm->size; + + return 0; +} +EXPORT_SYMBOL_NS_GPL(cxl_get_hdm_info, "CXL"); + #define CXL_DOE_TABLE_ACCESS_REQ_CODE 0x000000ff #define CXL_DOE_TABLE_ACCESS_REQ_CODE_READ 0 #define CXL_DOE_TABLE_ACCESS_TABLE_TYPE 0x0000ff00 diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 20c2d9fbcfe7..e828df0629d0 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -85,6 +85,7 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base, decoder_cnt = cxl_hdm_decoder_count(hdr); length = 0x20 * decoder_cnt + 0x10; rmap = &map->hdm_decoder; + rmap->count = decoder_cnt; break; } case CXL_CM_CAP_CAP_ID_RAS: diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index 802b143de83d..440ab09c640e 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -75,6 +75,7 @@ struct cxl_reg_map { int id; unsigned long offset; unsigned long size; + u8 count; }; struct cxl_component_reg_map { @@ -228,4 +229,7 @@ struct cxl_memdev *devm_cxl_probe_mem(struct cxl_dev_state *cxlds, struct range *range); int cxl_set_capacity(struct cxl_dev_state *cxlds, u64 capacity); + +int cxl_get_hdm_info(struct cxl_dev_state *cxlds, u8 *count, + resource_size_t *offset, resource_size_t *size); #endif /* __CXL_CXL_H__ */ -- 2.25.1