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Thu, 25 Jun 2026 09:55:15 -0700 From: To: , , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v3 05/11] vfio: UAPI for CXL Type-2 device passthrough Date: Thu, 25 Jun 2026 22:24:01 +0530 Message-ID: <20260625165407.1769572-6-mhonap@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260625165407.1769572-1-mhonap@nvidia.com> References: <20260625165407.1769572-1-mhonap@nvidia.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000209:EE_|CY8PR12MB8065:EE_ X-MS-Office365-Filtering-Correlation-Id: 1ecb2ca9-76e3-4570-ded3-08ded2da980c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700016|1800799024|23010399003|82310400026|6133799003|56012099006|11063799006|22082099003|18002099003|921020; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: hycrxyteLHEqd+iAjiKrgKJg7lmMYke6gd8dAGPA8nGJ4f/BwBihRsYSMFhSthcU0012R4ODscqXXqn5eUAMB38XV1QhzOoDcjgGD5vjhuAjjC2yb3WBNCIRuWzI67W0LpoqtlZiIz/rIDR4LLUUGP90y069Un7i1FnHefgMJVRq4Hf1mQ5PoCvty5nDvMUibt4skbX0U4SSpiI6E3Ad1+ql1uHumWMrnPMnDj0AWRfhTBs1o95HcT49COQZw85QnLbB41sn87LP4M8/jA/DBo0XKeD0NaO7GPNa0/JolgD2TrmBKjoh3DbRcfQPmbHsc6VhaiWj+hT6/B1dCvUb9TqA81fjUpXc3s6zehHvN4wN7j2b8iSbgx9OWou6YrSQMeZR5sDl72f43cnCF9bo2M8v3ZHnrc7O/S3Z/C4HeoYxNyAhDvWaFIbBGr49Su9o X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jun 2026 16:55:42.8623 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1ecb2ca9-76e3-4570-ded3-08ded2da980c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000209.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8065 From: Manish Honap Add the user-visible interface that exposes a CXL Type-2 device to a VMM through vfio-pci: VFIO_DEVICE_FLAGS_CXL (bit 9) on vfio_device_info::flags marks the device as CXL. VFIO_DEVICE_INFO_CAP_CXL (id 6) is the capability that carries the HDM-backed memory region index, the CXL component register region index, and the layout of the component register block within the containing PCI BAR. VFIO_REGION_SUBTYPE_CXL identifies the HDM memory region. VFIO_REGION_SUBTYPE_CXL_COMP_REGS identifies the CXL component register shadow. Only the HOST_FIRMWARE_COMMITTED flag is exposed. Other CXL device states stay invisible to userspace at this stage. Signed-off-by: Manish Honap --- include/uapi/linux/vfio.h | 46 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 5de618a3a5ee..3707d53c4de5 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -215,6 +215,7 @@ struct vfio_device_info { #define VFIO_DEVICE_FLAGS_FSL_MC (1 << 6) /* vfio-fsl-mc device */ #define VFIO_DEVICE_FLAGS_CAPS (1 << 7) /* Info supports caps */ #define VFIO_DEVICE_FLAGS_CDX (1 << 8) /* vfio-cdx device */ +#define VFIO_DEVICE_FLAGS_CXL (1 << 9) /* vfio-cxl Type-2 device */ __u32 num_regions; /* Max region index + 1 */ __u32 num_irqs; /* Max IRQ index + 1 */ __u32 cap_offset; /* Offset within info struct of first cap */ @@ -257,6 +258,36 @@ struct vfio_device_info_cap_pci_atomic_comp { __u32 reserved; }; +/* + * VFIO_DEVICE_INFO capability for CXL Type-2 passthrough devices. + * Present when VFIO_DEVICE_FLAGS_CXL is set on vfio_device_info::flags. + * + * @flags: VFIO_CXL_CAP_HOST_FIRMWARE_COMMITTED indicates the host CXL + * subsystem committed the endpoint HDM decoder. + * @hdm_region_idx: VFIO region index for the HDM memory region + * (subtype VFIO_REGION_SUBTYPE_CXL). + * @comp_reg_region_idx: VFIO region index for the CXL Component + * Register shadow (subtype VFIO_REGION_SUBTYPE_CXL_COMP_REGS). + * @comp_reg_bar: PCI BAR index that contains the CXL component + * register block. Get-region-info on this BAR returns a + * VFIO_REGION_INFO_CAP_SPARSE_MMAP that excludes the CXL block. + * @comp_reg_offset: byte offset of the CXL component register block + * within @comp_reg_bar. + * @comp_reg_size: byte size of the CXL component register block. + */ +#define VFIO_DEVICE_INFO_CAP_CXL 6 +struct vfio_device_info_cap_cxl { + struct vfio_info_cap_header header; + __u32 flags; +#define VFIO_CXL_CAP_HOST_FIRMWARE_COMMITTED (1 << 0) + __u32 hdm_region_idx; + __u32 comp_reg_region_idx; + __u32 comp_reg_bar; + __u32 __resv; + __u64 comp_reg_offset; + __u64 comp_reg_size; +}; + /** * VFIO_DEVICE_GET_REGION_INFO - _IOWR(VFIO_TYPE, VFIO_BASE + 8, * struct vfio_region_info) @@ -425,6 +456,21 @@ struct vfio_region_gfx_edid { #define VFIO_REGION_SUBTYPE_CCW_SCHIB (2) #define VFIO_REGION_SUBTYPE_CCW_CRW (3) +/* + * sub-types for VFIO_REGION_TYPE_PCI_VENDOR (vendor id 1e98 reserved + * for the CXL Consortium); used by vfio-cxl Type-2 device passthrough. + * + * VFIO_REGION_SUBTYPE_CXL exposes the HDM-backed device memory range + * as a mappable region. The range is allocated by the host CXL + * subsystem and the VMM is expected to mmap() it. + * VFIO_REGION_SUBTYPE_CXL_COMP_REGS exposes the CXL Component Register + * block (read-write via pread()/pwrite() only, no mmap()). The VMM + * reads and writes HDM Decoder Capability registers through this + * shadow region instead of touching hardware directly. + */ +#define VFIO_REGION_SUBTYPE_CXL (1) +#define VFIO_REGION_SUBTYPE_CXL_COMP_REGS (2) + /* sub-types for VFIO_REGION_TYPE_MIGRATION */ #define VFIO_REGION_SUBTYPE_MIGRATION_DEPRECATED (1) -- 2.25.1