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Thu, 25 Jun 2026 11:24:45 -0700 From: Shanker Donthineni To: Catalin Marinas , Will Deacon , Vladimir Murzin CC: Jason Gunthorpe , , Mark Rutland , , , Shanker Donthineni , Vikram Sethi , Jason Sequeira Subject: [PATCH v4 2/2] arm64: io: apply the device store-release workaround once per block write Date: Thu, 25 Jun 2026 13:24:25 -0500 Message-ID: <20260625182425.3194066-3-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260625182425.3194066-1-sdonthineni@nvidia.com> References: <20260625182425.3194066-1-sdonthineni@nvidia.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B372:EE_|SA1PR12MB6846:EE_ X-MS-Office365-Filtering-Correlation-Id: 8bfb0c3a-cff4-4ff4-a21c-08ded2e71657 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|23010399003|82310400026|376014|36860700016|56012099006|11063799006|6133799003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6BWzyKIEWI+erhqCTnqyXiVXcwlh5Q+3XgsukBqLI5tut++YOAT5Zn9ywdurtvxBBJdEULU09os20+6U9eR0JuqYOhEDLHZy04qmnqwPoyvCAj5qxmhw3WulGexyxxF/XDgEmzmJRoDT4Widh4CUOKQCQO9/sRZTMRJ/6uE7TeTbNHCKCLtW968fxiptRFSvPVkXsnrBAaftPHNCB5ULWHofsh3QxE5yMAvNStme84IjRmNvPBSp+vmoasp5ZU/e+UAvwFllczshYM4CyizmtBcj4AM9sxR4ejxJ32Ef7akES7tkVszakfk8oB7vktgAUJWBxRsdaWEbBKENCaThxRiy+lpj9uW3RP1obcj711BiOTkZ2TeDiiPWoCzOco9LiCCIykz6asW1QlccrJMXBE8nYPWDB5Nbkxy268uQfEY6nRCM7wadOYPA0yTg98PO X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jun 2026 18:25:08.5282 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8bfb0c3a-cff4-4ff4-a21c-08ded2e71657 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B372.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6846 The generic memset_io()/memcpy_toio() are built on __raw_write*(), so on parts with the NVIDIA Olympus device store/load ordering erratum the ARM64_WORKAROUND_DEVICE_STORE_RELEASE workaround promotes every store in the block to a store-release. Each stlr* carries a barrier cost, so block MMIO becomes O(n) store-releases, making a block copy many times slower than a single ordered burst and growing with the transfer size. Provide arm64 memset_io()/memcpy_toio() that emit plain str* in the loop and order the whole block against subsequent loads with a single trailing dmb osh on affected CPUs (a no-op elsewhere, preserving the relaxed contract of these helpers). This keeps block MMIO writes at one-barrier cost rather than scaling with the transfer size. Performance (NVIDIA Olympus, write-combining MMIO to a device BAR, single PE pinned; per-call cost in ns; consecutive writes ping-pong between two buffers so repeated stores are not coalesced; iowrite64/iowrite32 = __iowrite{64,32}_copy()): Table 1 - arm64 memset_io/memcpy_toio (this patch) +-------+-----------+-----------+-----------+-------------+ | size | iowrite64 | iowrite32 | memset_io | memcpy_toio | +-------+-----------+-----------+-----------+-------------+ | 8B | 231.6 ns | 231.6 ns | 232.4 ns | 232.4 ns | | 16B | 231.7 ns | 231.9 ns | 232.7 ns | 232.6 ns | | 32B | 231.9 ns | 232.7 ns | 232.9 ns | 232.9 ns | | 64B | 232.7 ns | 235.0 ns | 233.7 ns | 233.6 ns | | 128B | 233.6 ns | 235.8 ns | 234.4 ns | 234.3 ns | | 256B | 237.7 ns | 276.8 ns | 264.0 ns | 276.7 ns | | 512B | 237.7 ns | 277.1 ns | 238.1 ns | 277.6 ns | | 1KB | 253.7 ns | 279.3 ns | 276.1 ns | 294.1 ns | | 2KB | 295.0 ns | 318.7 ns | 288.5 ns | 308.3 ns | | 4KB | 365.9 ns | 381.4 ns | 365.7 ns | 381.3 ns | +-------+-----------+-----------+-----------+-------------+ all four helpers end with a single trailing barrier (dmb osh). Table 2 - generic per-store memset_io/memcpy_toio +-------+-----------+-----------+-------------+--------------+ | size | iowrite64 | iowrite32 | memset_io | memcpy_toio | +-------+-----------+-----------+-------------+--------------+ | 8B | 231.6 ns | 231.6 ns | 229.0 ns | 229.0 ns | | 16B | 231.7 ns | 231.9 ns | 458.4 ns | 458.5 ns | | 32B | 231.9 ns | 232.7 ns | 917.4 ns | 917.5 ns | | 64B | 232.7 ns | 234.8 ns | 1835.4 ns | 1835.5 ns | | 128B | 233.6 ns | 235.8 ns | 3670.9 ns | 3670.8 ns | | 256B | 237.7 ns | 276.7 ns | 7341.6 ns | 7341.6 ns | | 512B | 237.7 ns | 279.4 ns | 14001.4 ns | 14001.3 ns | | 1KB | 253.7 ns | 279.1 ns | 28631.5 ns | 28631.8 ns | | 2KB | 279.4 ns | 317.9 ns | 57276.3 ns | 57275.2 ns | | 4KB | 365.7 ns | 381.5 ns | 114564.4 ns | 114563.6 ns | +-------+-----------+-----------+-------------+--------------+ the generic memset_io()/memcpy_toio() build on __raw_write*(), which the workaround promotes to store-release, so every store is individually ordered - hence O(n) in the store count. The arm64 versions stay flat at one-barrier cost while the generic per-store writers collapse to O(n): at 4KB ~314x slower (~115 us vs ~366 ns). Signed-off-by: Shanker Donthineni --- arch/arm64/include/asm/io.h | 5 +++ arch/arm64/kernel/io.c | 82 +++++++++++++++++++++++++++++++++++++ 2 files changed, 87 insertions(+) diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h index 69e0fa004d31..649503f347bc 100644 --- a/arch/arm64/include/asm/io.h +++ b/arch/arm64/include/asm/io.h @@ -266,6 +266,11 @@ __iowrite64_copy(void __iomem *to, const void *from, size_t count) } #define __iowrite64_copy __iowrite64_copy +void memset_io(volatile void __iomem *dst, int c, size_t count); +#define memset_io memset_io +void memcpy_toio(volatile void __iomem *dst, const void *src, size_t count); +#define memcpy_toio memcpy_toio + /* * I/O memory mapping functions. */ diff --git a/arch/arm64/kernel/io.c b/arch/arm64/kernel/io.c index fe86ada23c7d..b5fd9ee6d9eb 100644 --- a/arch/arm64/kernel/io.c +++ b/arch/arm64/kernel/io.c @@ -5,9 +5,91 @@ * Copyright (C) 2012 ARM Ltd. */ +#include #include #include #include +#include + +#include + +/* + * ARM64_WORKAROUND_DEVICE_STORE_RELEASE promotes every raw MMIO store + * (__raw_write*()) to a store-release on affected CPUs. The generic + * memset_io()/memcpy_toio() are built on those helpers, so the workaround would + * emit one store-release per element and turn a block write into O(n) ordered + * stores - far more costly than the single barrier a block actually needs. + * + * Provide arm64 versions that emit plain STR in the loop and order the whole + * block against subsequent loads with one trailing DMB OSH, patched in only on + * affected CPUs (a no-op elsewhere, so the relaxed contract of these helpers is + * preserved). + * + * This capability is currently enabled only for the NVIDIA Olympus device + * store/load ordering erratum, where a Device-nGnR* load may be observed before + * an older, non-overlapping Device-nGnR* store to the same peripheral. + */ +static __always_inline void iomem_block_store_barrier(void) +{ + asm volatile(ALTERNATIVE("nop", "dmb osh", + ARM64_WORKAROUND_DEVICE_STORE_RELEASE) + : : : "memory"); +} + +void memset_io(volatile void __iomem *dst, int c, size_t count) +{ + u64 qc = (u8)c; + + qc *= ~0ULL / 0xff; + + while (count && !IS_ALIGNED((__force unsigned long)dst, sizeof(u64))) { + asm volatile("strb %w0, [%1]" : : "rZ"((u8)c), "r"(dst) : "memory"); + dst++; + count--; + } + while (count >= sizeof(u64)) { + asm volatile("str %x0, [%1]" : : "rZ"(qc), "r"(dst) : "memory"); + dst += sizeof(u64); + count -= sizeof(u64); + } + while (count) { + asm volatile("strb %w0, [%1]" : : "rZ"((u8)c), "r"(dst) : "memory"); + dst++; + count--; + } + + iomem_block_store_barrier(); +} +EXPORT_SYMBOL(memset_io); + +void memcpy_toio(volatile void __iomem *dst, const void *src, size_t count) +{ + while (count && !IS_ALIGNED((__force unsigned long)dst, sizeof(u64))) { + asm volatile("strb %w0, [%1]" + : : "rZ"(*(const u8 *)src), "r"(dst) : "memory"); + src++; + dst++; + count--; + } + while (count >= sizeof(u64)) { + asm volatile("str %x0, [%1]" + : : "rZ"(get_unaligned((const u64 *)src)), "r"(dst) + : "memory"); + src += sizeof(u64); + dst += sizeof(u64); + count -= sizeof(u64); + } + while (count) { + asm volatile("strb %w0, [%1]" + : : "rZ"(*(const u8 *)src), "r"(dst) : "memory"); + src++; + dst++; + count--; + } + + iomem_block_store_barrier(); +} +EXPORT_SYMBOL(memcpy_toio); /* * This generates a memcpy that works on a from/to address which is aligned to -- 2.54.0.windows.1