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From: Conor Dooley <conor@kernel.org>
To: Guodong Xu <docular.xu@gmail.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
	Shuah Khan <skhan@linuxfoundation.org>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>, Zong Li <zong.li@sifive.com>,
	Deepak Gupta <debug@rivosinc.com>,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <atish.patra@linux.dev>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Yixun Lan <dlan@kernel.org>,
	Chen Wang <unicorn_wang@outlook.com>,
	Inochi Amaoto <inochiama@gmail.com>,
	Chen Wang <chen.wang@linux.dev>,
	linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
	kvm-riscv@lists.infradead.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Jesse Taube <jtaubepe@redhat.com>,
	Charlie Jenkins <thecharlesjenkins@gmail.com>,
	Andrew Jones <andrew.jones@oss.qualcomm.com>,
	devicetree@vger.kernel.org, spacemit@lists.linux.dev,
	sophgo@lists.linux.dev, linux-kselftest@vger.kernel.org,
	Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v5 08/17] dt-bindings: riscv: Require block-size for Zicbom, Zicbop, and Zicboz
Date: Wed, 1 Jul 2026 21:39:19 +0100	[thread overview]
Message-ID: <20260701-squiggle-aging-459cd99cb2dc@spud> (raw)
In-Reply-To: <20260701-rva23u64-hwprobe-v2-v5-8-2c61f94a695a@gmail.com>

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On Wed, Jul 01, 2026 at 08:52:21AM -0400, Guodong Xu wrote:
> Zicbom, Zicbop, and Zicboz have no default cache block size, so a
> devicetree that declares one must also provide the matching
> riscv,cbom/cbop/cboz-block-size property. Make it required so a
> missing block-size property can be caught by dtbs_check.
> 
> Suggested-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Guodong Xu <docular.xu@gmail.com>
> ---
> v5: New patch.
> ---
>  .../devicetree/bindings/riscv/extensions.yaml      | 26 ++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 5ffc40d599c02..f4dd34d446c02 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -1142,6 +1142,32 @@ allOf:
>            not:
>              contains:
>                const: zilsd
> +  # All three Zicbo* extensions require their block size property as there's no
> +  # default.
> +  - if:
> +      properties:
> +        riscv,isa-extensions:
> +          contains:
> +            const: zicbom

I think the way to fix this is to add
  required:
    - riscv,isa-extensions
to each of these if conditions
(not got time to test it right now, sorry)

> +    then:
> +      required:
> +        - riscv,cbom-block-size
> +  - if:
> +      properties:
> +        riscv,isa-extensions:
> +          contains:
> +            const: zicbop
> +    then:
> +      required:
> +        - riscv,cbop-block-size
> +  - if:
> +      properties:
> +        riscv,isa-extensions:
> +          contains:
> +            const: zicboz
> +    then:
> +      required:
> +        - riscv,cboz-block-size
>  
>  additionalProperties: true
>  ...
> 
> -- 
> 2.43.0
> 

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  parent reply	other threads:[~2026-07-01 20:39 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-01 12:52 [PATCH v5 00/17] riscv: hwprobe: Expose RVA23U64 base behavior Guodong Xu
2026-07-01 12:52 ` [PATCH v5 01/17] dt-bindings: riscv: sort multi-letter Z extensions alphanumerically Guodong Xu
2026-07-01 12:52 ` [PATCH v5 02/17] riscv: hwprobe.rst: Make indentation consistent Guodong Xu
2026-07-01 12:52 ` [PATCH v5 03/17] riscv: hwprobe.rst: Document EXT_ZICFISS and EXT_ZICFILP Guodong Xu
2026-07-01 12:52 ` [PATCH v5 04/17] riscv: Standardize extension capitalization Guodong Xu
2026-07-01 12:52 ` [PATCH v5 05/17] riscv: Add Zicclsm to cpufeature and hwprobe Guodong Xu
2026-07-01 12:52 ` [PATCH v5 06/17] riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs " Guodong Xu
2026-07-01 12:52 ` [PATCH v5 07/17] riscv: Add B to hwcap " Guodong Xu
2026-07-01 12:52 ` [PATCH v5 08/17] dt-bindings: riscv: Require block-size for Zicbom, Zicbop, and Zicboz Guodong Xu
2026-07-01 15:54   ` Rob Herring (Arm)
2026-07-01 20:39   ` Conor Dooley [this message]
2026-07-01 12:52 ` [PATCH v5 09/17] dt-bindings: riscv: Add Zic64b extension description Guodong Xu
2026-07-01 12:52 ` [PATCH v5 10/17] riscv: Add Zic64b to cpufeature and hwprobe Guodong Xu
2026-07-01 12:52 ` [PATCH v5 11/17] riscv: dts: spacemit: k3: Add Zic64b ISA extension Guodong Xu
2026-07-01 12:52 ` [PATCH v5 12/17] riscv: dts: spacemit: k1: " Guodong Xu
2026-07-01 12:52 ` [PATCH v5 13/17] riscv: dts: sophgo: sg2044: " Guodong Xu
2026-07-01 12:52 ` [PATCH v5 14/17] riscv: Add a getter for user PMLEN support Guodong Xu
2026-07-01 12:52 ` [PATCH v5 15/17] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection Guodong Xu
2026-07-01 12:52 ` [PATCH v5 16/17] riscv: cpu: Output isa bases lines in cpuinfo Guodong Xu
2026-07-01 12:52 ` [PATCH v5 17/17] riscv: hwprobe: Introduce rva23u64 base behavior Guodong Xu

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