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Sun, 05 Jul 2026 07:01:07 -0700 (PDT) From: Tomer Maimon To: andrew@codeconstruct.com.au, wim@linux-watchdog.org, linux@roeck-us.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: openbmc@lists.ozlabs.org, linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com, corbet@lwn.net, skhan@linuxfoundation.org, joel@jms.id.au Subject: [PATCH v3 1/3] dt-bindings: watchdog: npcm: add GCR syscon property Date: Sun, 5 Jul 2026 17:00:58 +0300 Message-Id: <20260705140100.1543486-2-tmaimon77@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260705140100.1543486-1-tmaimon77@gmail.com> References: <20260705140100.1543486-1-tmaimon77@gmail.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit NPCM750 and NPCM845 latch watchdog reset indications in the SoC GCR block rather than in the watchdog block itself. Add the optional nuvoton,sysgcr phandle so watchdog nodes can reference the shared GCR reset-status registers that hold those latched watchdog reset indications. This is needed by the following reset-status support, which reads those latches and reports watchdog-caused resets through bootstatus. Signed-off-by: Tomer Maimon --- .../devicetree/bindings/watchdog/nuvoton,npcm750-wdt.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm750-wdt.yaml b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm750-wdt.yaml index 7aa30f5b5c49..99c225f166db 100644 --- a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm750-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm750-wdt.yaml @@ -40,6 +40,12 @@ properties: clock-frequency: description: Frequency in Hz of the clock that drives the NPCM timer. + nuvoton,sysgcr: + $ref: /schemas/types.yaml#/definitions/phandle + description: + a phandle to access the GCR reset-status registers that latch + watchdog reset indications on NPCM750 and NPCM845. + required: - compatible - reg -- 2.34.1