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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ1PEPF0000231F.mail.protection.outlook.com (10.167.242.235) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.245.5 via Frontend Transport; Fri, 17 Jul 2026 22:29:19 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Fri, 17 Jul 2026 17:29:18 -0500 From: Terry Bowman To: Bjorn Helgaas , Dan Williams , "Dave Jiang" , Ira Weiny , Jonathan Cameron , Len Brown , "Rafael J . Wysocki" , Robert Richter CC: , , , , , , "Alejandro Lucero" , Alison Schofield , Ankit Agrawal , Ard Biesheuvel , "Ben Cheatham" , Borislav Petkov , "Breno Leitao" , Davidlohr Bueso , "Fabio M . De Francesco" , Gregory Price , Hanjun Guo , Jonathan Corbet , Kees Cook , Kuppuswamy Sathyanarayanan , Li Ming , Mahesh J Salgaonkar , Mauro Carvalho Chehab , Oliver O'Halloran , Shiju Jose , Shuah Khan , Shuai Xue , Smita Koralahalli , Terry Bowman , Tony Luck , Vishal Verma Subject: [PATCH v18 11/13] PCI: Cache PCI DSN into pci_dev->dsn during probe Date: Fri, 17 Jul 2026 17:27:04 -0500 Message-ID: <20260717222706.3540281-12-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com> References: <20260717222706.3540281-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231F:EE_|BL3PR12MB6521:EE_ X-MS-Office365-Filtering-Correlation-Id: bb52cb4c-8a01-4a4a-cf78-08dee452d839 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|7416014|23010399003|376014|1800799024|6133799003|56012099006|11063799006|10067099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: cvD165g+fkhnl5f+WuX7JbhIbItD4yFE2+gvGB0MyW7BXddHmNJBzxCi0iqihzWFK5m2nhJnrj5aogVfhVA4zT0G/IFFn/mbV5RcWeRAmG7dO3hM8OaOZ3Iv5M28JlJQnvr6kW2PRW3+b91BVw4soGDQw7YIZMl9GYA8fmOHB+gsKhD1yU4HUqpvqX7mfJknboMsCA4b9LQD5BlhT3t/ylrg8emrpjlZC0bdgKClVl/Ju1+awgSZa50CE9teI/sXk6RCcHIABjwf3FoS7u9hjWcolVuqw1haoqULRo2em9otjCQ0KeCHPvZ6aSy6Y6Kqkt7Ynwdwq6fbYtpcoRFwTMd6t+fnfwJ8ut3hckdzR7ugjMX4DJpzF9ObzC899HihdLKiqQMZJFuJ8ws2R/pwBGQFUrRBlPW1yfwRWuQi+RyFRMNFCDu/tGhdRCFQDkfloTkuy6Pdg6ptEgvUuWDhfa7SAOereAydp/PMCNT1iiX5kDars44Edm/JodUPQoi8MbNZxQBZIrTTywUcCJunaMw5RFiDLuMhdWm1iMJ36B6CyRjWedc/HR2rU+iKv4B7U43QwmoRHLtVs4D7NrlGEA/g4QDYAb8rt4qk7VwVlwVbEGtc+T2lSiiJWLX/NTDROo6xibLCa17tUn01wWeJ3EOzSWGs3j+AK0QN73EQ46xoFtlJjpM6K9oMmCo5dFmPCZuTEm8cAQqSOLTmEdug8g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(7416014)(23010399003)(376014)(1800799024)(6133799003)(56012099006)(11063799006)(10067099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: gMrsoUE2T3tLHTULWXF85fweqnd0xsAkr4bsR+YRcTTby6yzq6x5PQ0cpvReR0Fzu+hQM0gQ6gTFQNglaHvowLoOXVqN5dNwQpsmo6VRTBwgEacvMZR0VtPufgCw3WabvRuRwCeHq28ypw0U3ZOLnOU+yrH+aztQwV1+KZUOLkaCs25wzVp/SP6DzOb9O6L0wZ4rzmoaMUEwOdm0GajaHql6sAK62sX2/8BCmPLXUiz+VZ84w9ELFBnTXblD33XUNJMYKMhT5KpYsXH4bLng001uijAAg7P/KHTpJ6ucot0PRfMky96mL9XomeKb7+EQyJ9rD7QgmE0Cd7BR0Oj8WLStU1aZ1lNy3FZbmRvNj06UeVylATp1pQ6HoRmzzIg/2fHQ5fnOm4z5lm3QhgxFtZrUEMgvpPHXsnKvKawpOrH8xI308yzQBRtKZJEAtKcx X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2026 22:29:19.8037 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bb52cb4c-8a01-4a4a-cf78-08dee452d839 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6521 Subsequent CXL error-reporting code paths need to log the PCI Device Serial Number (DSN) as part of trace events emitted from interrupt or panic context. Computing the DSN there via pci_get_dsn() requires PCI configuration space reads, which are slow, can fail when the link is down or frozen, and may not be safe in some contexts. Add a u64 dsn field to struct pci_dev and populate it from pci_get_dsn() during pci_init_capabilities() at probe time via pci_dsn_init(). Only write dev->dsn when the read succeeds. The zero initial value from pci_dev allocation already represents 'no DSN available.' pci_get_dsn() is not modified because it remains a pure config-space read with no side effects on pci_dev. The cache is written exclusively by pci_dsn_init() at probe time. Signed-off-by: Terry Bowman --- Changes in v17->v18: - New commit. --- drivers/cxl/core/ras.c | 11 ++++++----- drivers/cxl/core/ras_rch.c | 4 ++-- drivers/cxl/pci.c | 2 +- drivers/pci/probe.c | 14 ++++++++++++++ include/linux/pci.h | 1 + 5 files changed, 24 insertions(+), 8 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index acf40b2396c3b..69b320c74469c 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -100,10 +100,10 @@ void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data) dport = cxl_find_dport_by_dev(port, &pdev->dev); if (data->severity == AER_CORRECTABLE) - cxl_cper_trace_corr_prot_err(port, dport, pci_get_dsn(pdev), + cxl_cper_trace_corr_prot_err(port, dport, pdev->dsn, &data->ras_cap); else - cxl_cper_trace_uncorr_prot_err(port, dport, pci_get_dsn(pdev), + cxl_cper_trace_uncorr_prot_err(port, dport, pdev->dsn, &data->ras_cap); } EXPORT_SYMBOL_GPL(cxl_cper_handle_prot_err); @@ -195,7 +195,7 @@ void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port, struct cxl_dpo return; } - if (cxl_handle_ras(port, dport, ras_base, pci_get_dsn(pdev))) + if (cxl_handle_ras(port, dport, ras_base, pdev->dsn)) panic("CXL cachemem error"); dev_dbg(&pdev->dev, @@ -307,7 +307,7 @@ pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, * CXL.mem traffic. */ ue = cxl_handle_ras(port, NULL, to_ras_base(port, NULL), - pci_get_dsn(pdev)); + pdev->dsn); } /* @@ -339,7 +339,8 @@ static void cxl_handle_proto_error(struct pci_dev *pdev, struct cxl_port *port, struct cxl_dport *dport, int severity) { if (severity == AER_CORRECTABLE) - cxl_handle_cor_ras(port, dport, to_ras_base(port, dport), pci_get_dsn(pdev)); + cxl_handle_cor_ras(port, dport, to_ras_base(port, dport), + pdev->dsn); else cxl_do_recovery(pdev, port, dport); } diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c index 0385d2f4a2f66..14bb3bdb2d092 100644 --- a/drivers/cxl/core/ras_rch.c +++ b/drivers/cxl/core/ras_rch.c @@ -118,8 +118,8 @@ void cxl_handle_rdport_errors(struct pci_dev *pdev) pci_print_aer(pdev, severity, &aer_regs); if (severity == AER_CORRECTABLE) - cxl_handle_cor_ras(dport->port, dport, to_ras_base(port, dport), - pci_get_dsn(pdev)); + cxl_handle_cor_ras(dport->port, dport, + to_ras_base(port, dport), pdev->dsn); else cxl_do_recovery(pdev, dport->port, dport); } diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 6cf1db7b85020..45a994cc782a9 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -807,7 +807,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (!dvsec) pci_warn(pdev, "Device DVSEC not present, skip CXL.mem init\n"); - mds = cxl_memdev_state_create(&pdev->dev, pci_get_dsn(pdev), dvsec); + mds = cxl_memdev_state_create(&pdev->dev, pdev->dsn, dvsec); if (IS_ERR(mds)) return PTR_ERR(mds); cxlds = &mds->cxlds; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index dd0abbc63e18d..92ece5ec211f8 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2638,6 +2638,19 @@ void pcie_report_downtraining(struct pci_dev *dev) __pcie_print_link_status(dev, false); } +/* + * Cache the Device Serial Number for use in contexts where config-space + * reads are unsafe (interrupt, panic). Process-context callers that + * need a fresh value (e.g. hotplug device replacement) use pci_get_dsn(). + */ +static void pci_dsn_init(struct pci_dev *dev) +{ + u64 dsn = pci_get_dsn(dev); + + if (dsn) + dev->dsn = dsn; +} + static void pci_imm_ready_init(struct pci_dev *dev) { u16 status; @@ -2674,6 +2687,7 @@ static void pci_init_capabilities(struct pci_dev *dev) pci_rebar_init(dev); /* Resizable BAR */ pci_dev3_init(dev); /* Device 3 capabilities */ pci_ide_init(dev); /* Link Integrity and Data Encryption */ + pci_dsn_init(dev); /* Serial number */ pcie_report_downtraining(dev); pci_init_reset_methods(dev); diff --git a/include/linux/pci.h b/include/linux/pci.h index 64b308b6e61c1..48a1622639190 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -386,6 +386,7 @@ struct pci_dev { unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ struct pci_driver *driver; /* Driver bound to this device */ + u64 dsn; /* PCI Device Serial Number */ u64 dma_mask; /* Mask of the bits of bus address this device implements. Normally this is 0xffffffff. You only need to change -- 2.34.1