From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0ADD2D8379; Mon, 20 Jul 2026 21:26:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784582786; cv=none; b=jSPTjyIQoUo+tso/hOhGew3C4hzbdVFTB+wl+a6CKwEV9WMLbuCbJDIN6Z3ox/374fqv11NUuzGWByHbLeOA6amBrQh5J9LjLQAEZ7tky2dNLRG9jXW5oBKCrA46J/RvdfJfsvvNROkPSQu29u+Y6amPwXfqgLx1b7tDQHvMznU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784582786; c=relaxed/simple; bh=VwBOnFkIHuj1oja64Y6Me7RM7wIS0U1e83LuPKLzueo=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KacD35mTJoy3yhXoLx1ZZJ+/eETbSaqhNG2I5M7UTWkxNEpoKPWgYdI7QIvXy42cHn5brOWPngHWBE32Lijvf43OiZOJEQqQcUbKirwDaKXZvQHlTFYL7pCe4BsDBZTdfp7MJ0JezDP1dCRcp3klZtRLd/Lsn6G8jtKY8bFgFBo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=knv+WWyz; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="knv+WWyz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 56A221F000E9; Mon, 20 Jul 2026 21:26:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784582784; bh=hgzEzv8KzgA973IVv/uKk4z9kYIa69UBaICYLVX6RMg=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=knv+WWyzLr/C2po5DrcJFrX9FdjRP9H+TlZLo1CLUoIgIpyhO82mKxuQdkEmibVlz jX6p05F1rxsZFJd4bkrUl4RnpeVF2D6iJkvChjuJDDxsw6DxVmXkb1WN1iS4FZJ4E4 yFRdFayH9GnyH9dlNK2ROKWXjkRS9klUCMYl2Qjio8Xiq6eZ9wogLMx/jboQKLWWN4 kgAZDqRiP2JyGH2uvgQrV6wWsNQWxkkonhwHfFdYV8mTUkG6k/Og/vd/22Z1Gblm+p V7b81n6qwDfZYdZsx64YW+aUgqrb7XeoEggT/vHCrrTiUPoyNKop5lfX9Q6Mq5MMHU eaYv04sBAePUA== Date: Mon, 20 Jul 2026 22:26:17 +0100 From: Jonathan Cameron To: Terry Bowman Cc: Bjorn Helgaas , Dan Williams , "Dave Jiang" , Ira Weiny , Len Brown , "Rafael J . Wysocki" , Robert Richter , , , , , , , "Alejandro Lucero" , Alison Schofield , Ankit Agrawal , Ard Biesheuvel , "Ben Cheatham" , Borislav Petkov , "Breno Leitao" , Davidlohr Bueso , "Fabio M . De Francesco" , Gregory Price , Hanjun Guo , Jonathan Corbet , Kees Cook , Kuppuswamy Sathyanarayanan , Li Ming , Mahesh J Salgaonkar , Mauro Carvalho Chehab , Oliver O'Halloran , Shiju Jose , Shuah Khan , Shuai Xue , Smita Koralahalli , Tony Luck , Vishal Verma Subject: Re: [PATCH v18 01/13] cxl/ras: Fix cxl_rch_get_aer_severity() wrong severity register Message-ID: <20260720222617.29d5676c@jic23-huawei> In-Reply-To: <20260717222706.3540281-2-terry.bowman@amd.com> References: <20260717222706.3540281-1-terry.bowman@amd.com> <20260717222706.3540281-2-terry.bowman@amd.com> X-Mailer: Claws Mail 4.4.0 (GTK 3.24.52; x86_64-pc-linux-gnu) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Fri, 17 Jul 2026 17:26:54 -0500 Terry Bowman wrote: > cxl_rch_get_aer_severity() classifies RCH Downstream Port uncorrectable > errors as fatal or non-fatal by ANDing uncorrectable status with > PCI_ERR_ROOT_FATAL_RCV. This is wrong because PCI_ERR_ROOT_FATAL_RCV is a > Root Error Status register bit (bit 6), not a severity bit. ANDing it > against uncorrectable status tests a reserved bit and produces incorrect > severity classification. > > Fix by ANDing the unmasked uncor_status against uncor_severity. Per > PCIe Base Spec r6.0 Section 7.8.4.4, each bit in the Uncorrectable > Error Severity register indicates whether the corresponding error is > fatal (1) or non-fatal (0). > > Fixes: 6ac07883dbb5 ("cxl/pci: Add RCH downstream port error logging") > Cc: stable@vger.kernel.org > Signed-off-by: Terry Bowman > One trivial thing below, otherwise LGTM Either way Reviewed-by: Jonathan Cameron > --- > > Changes in v17 -> v18: > - New patch. > --- > drivers/cxl/core/ras_rch.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c > index 0a8b3b9b63884..44b335d560708 100644 > --- a/drivers/cxl/core/ras_rch.c > +++ b/drivers/cxl/core/ras_rch.c > @@ -80,7 +80,8 @@ static bool cxl_rch_get_aer_severity(struct aer_capability_regs *aer_regs, > int *severity) > { > if (aer_regs->uncor_status & ~aer_regs->uncor_mask) { > - if (aer_regs->uncor_status & PCI_ERR_ROOT_FATAL_RCV) > + if ((aer_regs->uncor_status & ~aer_regs->uncor_mask) & This bit looks familiar (see line above!) Worth a local variable maybe? > + aer_regs->uncor_severity) > *severity = AER_FATAL; > else > *severity = AER_NONFATAL;