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Sun, 26 Jul 2026 01:19:07 -0700 From: Ashish Mhetre To: , , , , , , , CC: , , , , , Ashish Mhetre Subject: [PATCH v9 4/4] iommu/arm-smmu-v3: Enable CFGI/TLBI-repeat workaround on Tegra264 Date: Sun, 26 Jul 2026 08:19:04 +0000 Message-ID: <20260726081904.1408859-5-amhetre@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260726081904.1408859-1-amhetre@nvidia.com> References: <20260726081904.1408859-1-amhetre@nvidia.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW1PEPF0001615C:EE_|DS0PR12MB9273:EE_ X-MS-Office365-Filtering-Correlation-Id: b0be5588-513e-46ad-0040-08deeaee9475 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|7416014|82310400026|1800799024|36860700016|56012099006|10067099003|11063799006|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: XtN0WlXc5cY9hdIODN9RkF7q64PGSRAuQmBVnuqeeD8uzX+JVPZ4VROa2yWhJ85T+bmOWJfPRCVp6npQz6RF2gYzzwYvg9Czp3J0L+9Ji/S6BeXf++tuCBEbFL5tACrPfiAOGUtYhL1O9MngOyZRLZUFO3XowRNhZETesaZBb9D4wFrrvivtHcNNVZfx+t7z0CvTwMK3kYicyKocJOuEAcBc6kRp2+kEbTgw5VCweLcO25wLfxCY7T6y6q1vN+PsTEghgeQZs0s7i4KV2U+4HT055PBRmzIq8KK0XGX4CWzWKhHxk9pWwpybdPC8ZWhUl5KXP2HyYj+POK8WsJzwdBz9AeP0mPTqqrTVIaDpLV3se7eWdB+xJ7AIx+6UXpzmxY2kgmOUrn0bhnDoh/rTND15n4SNP2kT3YE9vU/XPFqr6UCtS5ycJA4IvCUuUUef X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jul 2026 08:19:14.5989 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b0be5588-513e-46ad-0040-08deeaee9475 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MW1PEPF0001615C.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9273 Nvidia Tegra264 SMMU is affected by an erratum where a TLB entry can survive an invalidation that races with concurrent traffic targeting the same entry. The hardware-recommended software workaround is to issue every CFGI/TLBI command (each followed by CMD_SYNC) twice, and that infrastructure is already in place behind arm_smmu_erratum_repeat_tlbi_cfgi_key. Neither IDR nor IIDR flags this Tegra264-specific bug, so hardware detection is not possible. Tegra264 is device-tree-only (no ACPI/IORT support) and already has a dedicated "nvidia,tegra264-smmu" compatible, so DT-probe is the only viable detection path. Enable the workaround on instances matching the existing "nvidia,tegra264-smmu" compatible by calling static_branch_enable() on arm_smmu_erratum_repeat_tlbi_cfgi_key. Document the erratum in Documentation/arch/arm64/silicon-errata.rst. Signed-off-by: Ashish Mhetre --- Documentation/arch/arm64/silicon-errata.rst | 2 ++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index 868bd9eed9a6..36c7b6c8b4e3 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -318,6 +318,8 @@ stable kernels. | | | T241-MPAM-4, | | | | | T241-MPAM-6 | | +----------------+-----------------+-----------------+-----------------------------+ +| NVIDIA | T264 SMMU | T264-SMMU-3 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+ | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | +----------------+-----------------+-----------------+-----------------------------+ diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index f9f2f47e0ffc..2096470a2477 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -5391,8 +5391,10 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev, if (of_dma_is_coherent(dev->of_node)) smmu->features |= ARM_SMMU_FEAT_COHERENCY; - if (of_device_is_compatible(dev->of_node, "nvidia,tegra264-smmu")) + if (of_device_is_compatible(dev->of_node, "nvidia,tegra264-smmu")) { tegra_cmdqv_dt_probe(dev->of_node, smmu); + static_branch_enable(&arm_smmu_erratum_repeat_tlbi_cfgi_key); + } return ret; } -- 2.50.1