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Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/ad7768.pdf **Device Overview:** The AD7768 is an 8-channel, 24-bit simultaneous sampling ADC. The AD7768-4 is a 4-channel variant. Both support configurable power modes, programmable decimation filters, and a high-speed serial interface with 1, 2, 4, or 8 data output lines. Per-channel offset, gain, and phase calibration registers are available. **Features Implemented:** - Support for AD7768 (8-channel) and AD7768-4 (4-channel) via device match data. - Automatic low-noise power mode selection (fast, median, low power) with associated decimation rate and output data rate tables. - Per-channel offset, gain, and conversion delay via IIO attributes. - SPI communication with custom regmap bus for the device's protocol. - IIO backend integration with adi-axi-adc for high-speed data capture. - CRC data integrity verification over the serial interface. - GPIO auxiliary driver to expose the 5 on-chip GPIO pins. - VCM common-mode output exposed through the regulator framework, with runtime PM management while the output is enabled. **Patch Summary:** 1. **dt-bindings**: Binding documentation for AD7768 and AD7768-4, covering SPI interface, clock, power supplies, reference voltage, reset GPIO, serial data lane count, and on-chip GPIO controller. 2. **iio: backend**: Add CRC enable/disable backend operation for data integrity verification over the high-speed serial interface. 3. **iio: adi-axi-adc**: Implement the new CRC backend operation. 4. **driver**: Core IIO driver for AD7768/AD7768-4 with regmap, power mode, calibration, and IIO backend support. Registers an auxiliary device to expose the GPIO functionality. 5. **gpio: regmap**: Add optional runtime PM integration and support for reading output values from a separate register. 6. **gpio**: Auxiliary bus GPIO driver for the AD7768's 5 general-purpose I/O pins, reusing the parent's regmap and runtime PM. 7. **docs**: Driver documentation. **Testing:** The driver was compiled and tested on the EVAL-AD7768FMCZ using a Zedboard with a mainline kernel. **Driver Rationale:** The AD7768/AD7768-4 warrants its own driver due to several device-specific characteristics: 1. A custom SPI framing protocol: register reads and writes use 16-bit frames with embedded read/write bits and register address fields, requiring a custom regmap bus implementation rather than the standard SPI regmap backend. 2. A coupled power mode / sample rate model: available output data rates are not a flat list but depend on the active power mode (fast, median, low power), each with its own set of valid decimation rates. This relationship must be managed in the driver. 3. Simultaneous sampling across all channels with per-channel calibration registers (24-bit offset, gain, and phase) that are laid out differently between the 8-channel AD7768 and the 4-channel AD7768-4, requiring device-specific register mapping. 4. IIO backend integration for high-speed data capture via adi-axi-adc, including CRC data integrity verification over the serial interface. 5. On-chip GPIO: 5 general-purpose I/O pins exposed via an auxiliary bus driver, sharing the parent's regmap and runtime PM. Signed-off-by: Janani Sunil --- Changes in v2: - Renamed and expanded supply descriptions, split reference to ref1-supply and ref2-supply. - Added START and synchronization signal descriptions. - Added variant-specific channel and data-line validation. - Made adi,data-lines-number optional, defaulting to the maximum. - Renamed the precharge and reference-buffer properties, removed channel mode and power mode properties. - Exposed the VCM output through the regulator framework and updated documentation accordingly. - Improved runtime PM initialization and requested initial autosuspend after probe. - Automatically assigned channels to two hardware mode profiles. - Selected the lowest noise compatible power mode when ODR ranges overlap. - Replaced the raw phase attribute with the standard conversion-delay attribute. - Added filter-settling delays based on the selected filter and ODR. - Fixed AD7768-4 register and channel-bit mapping, including standby, calibration, phase, precharge and reference-buffer handling. - Added direct-mode protection around runtime channel configuration. - Added calibration register range validation and documented calibration values as raw unsigned 24-bit values. - Added the required reset pulse delay derived from MCLK. - Added a generic GPIO-regmap patch providing runtime-PM integration and separate output-register readback. - Converted the AD7768 GPIO auxiliary driver to use gpio-regmap. - Documented that AXI ADC CRC control bit 8 is common to the AXI ADC cores. - Added the missing AXI ADC mutex initialization. - Expanded the driver documentation to describe dynamic channel grouping, power-mode selection, VCM regulation and conversion delay. - Link to v1: https://lore.kernel.org/r/20260709-ad7768-driver-v1-0-44e1194fd96a@analog.com --- Janani Sunil (7): dt-bindings: iio: adc: Add AD7768 iio: backend: Add support for CRC iio: adc: adi-axi-adc: Add support for CRC iio: adc: Add AD7768 IIO Driver support gpio: regmap: Add runtime PM and read_output_reg_set support gpio: ad7768: Add AD7768 GPIO auxiliary driver Documentation: iio: Add AD7768 Documentation .../devicetree/bindings/iio/adc/adi,ad7768.yaml | 343 ++++ Documentation/iio/ad7768.rst | 240 +++ Documentation/iio/index.rst | 1 + MAINTAINERS | 10 + drivers/gpio/Kconfig | 12 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-ad7768.c | 78 + drivers/gpio/gpio-regmap.c | 113 +- drivers/iio/adc/Kconfig | 16 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad7768.c | 1720 ++++++++++++++++++++ drivers/iio/adc/adi-axi-adc.c | 26 + drivers/iio/industrialio-backend.c | 33 + include/linux/gpio/regmap.h | 8 + include/linux/iio/backend.h | 6 + 15 files changed, 2592 insertions(+), 16 deletions(-) --- base-commit: b75697ef53e435d894833dad2a8c2fa882cb9b19 change-id: 20260708-ad7768-driver-10cd15296c20 Best regards, -- Janani Sunil