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Signed-off-by: Janani Sunil --- .../devicetree/bindings/iio/adc/adi,ad7768.yaml | 338 +++++++++++++++++++++ MAINTAINERS | 7 + 2 files changed, 345 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7768.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7768.yaml new file mode 100644 index 000000000000..54241436f47f --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7768.yaml @@ -0,0 +1,338 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad7768.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD7768 and AD7768-4 ADC + +maintainers: + - Janani Sunil + +description: | + The AD7768 is an 8-channel, 24-bit simultaneous sampling ADC with configurable + power and performance modes. The AD7768-4 is a 4-channel version. + + This binding covers SPI mode only (register access via SPI). Pin control mode, + where configuration is set via hardware pins rather than SPI registers, is not + supported. + + The io-backend represents the high-speed data output interface, consuming the + DOUTx data lines, DCLK (data clock), and DRDY (data ready) signals. + + Datasheet at: + https://www.analog.com/media/en/technical-documentation/data-sheets/ad7768.pdf + + HDL reference design: + https://github.com/analogdevicesinc/hdl/tree/main/projects/ad7768evb + +properties: + compatible: + enum: + - adi,ad7768 + - adi,ad7768-4 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: + Master clock (MCLK). Can be supplied as a CMOS clock on the XTAL2/MCLK + pin, a crystal oscillator connected between the XTAL1 and XTAL2 pins, or + an LVDS differential clock on the XTAL1/XTAL2 pin pair. The clock source + is selected by the CLK_SEL hardware pin. + + avdd1-supply: + description: + Analog supply voltage for the AVDD1A and AVDD1B pins (5V ± 10% with + respect to AVSS). Powers the analog front end, reference input, and + common-mode output circuitry. Both pins must be tied to the same + potential. + + avss-supply: + description: + Negative analog supply rail for the AVSS1A, AVSS1B, AVSS2A, AVSS2B, + and AVSS pins. This rail is referenced to DGND and all AVSS pins must + be tied to the same potential. In single-supply operation AVSS is + nominally 0V; in split-supply operation it can range from 0V to + -2.75V with respect to DGND. + + avdd2-supply: + description: + Analog supply voltage for the AVDD2A and AVDD2B pins (2V to 5.5V with + respect to AVSS). Connects to internal 1.8V analog LDO regulators that + power the ADC core. Both pins must be tied to the same potential. + + iovdd-supply: + description: + Digital supply voltage IOVDD (2.25V to 3.6V with respect to DGND). + Sets the logic levels for all interface pins and powers the digital + processing core via an internal LDO. For 1.8V operation (1.72V to + 1.88V), IOVDD must be tied to the DREGCAP pin. + + ref1-supply: + description: + Differential reference voltage supply for the REF1+/REF1- input pair. + REF1+ voltage range is from (AVSS + 1V) to AVDD1; REF1- voltage range + is from AVSS to (AVDD1 - 1V). The differential reference voltage range + is 1V to |AVDD1 - AVSS|. On the AD7768 this reference is used for + channels 0 to 3; on the AD7768-4 for channels 0 and 1. + + ref2-supply: + description: + Differential reference voltage supply for the REF2+/REF2- input pair. + REF2+ voltage range is from (AVSS + 1V) to AVDD1; REF2- voltage range + is from AVSS to (AVDD1 - 1V). The differential reference voltage range + is 1V to |AVDD1 - AVSS|. On the AD7768 this reference is used for + channels 4 to 7; on the AD7768-4 for channels 2 and 3. + + reset-gpios: + maxItems: 1 + description: GPIO connected to the active-low RESET pin + + start-gpios: + maxItems: 1 + description: + GPIO connected to the START pin. An active-low pulse on this pin + synchronizes the device to other AD7768 devices. When not used, this + pin must be tied to a logic high level through a pull-up resistor. + When used, SYNC_OUT must be wired back to SYNC_IN on all devices in + the synchronization chain. + + sync-in-gpios: + maxItems: 1 + description: + GPIO connected to the SYNC_IN pin. Receives the synchronization pulse + generated on SYNC_OUT in response to a START pulse. Must be synchronous + to the MCLK clock domain. In multi-device or daisy-chained systems, + two successive synchronization pulses must be applied to guarantee all + ADCs are synchronized. + + sync-out-gpios: + maxItems: 1 + description: + GPIO connected to the SYNC_OUT pin. Outputs a synchronization pulse + synchronous to MCLK in response to a START pulse or SPI_SYNC command. + In single-device configurations this pin must be wired back to SYNC_IN. + In multi-device configurations it can be routed to the SYNC_IN pins of + all devices in the chain. + + gpio-controller: true + + '#gpio-cells': + const: 2 + + adi,data-lines-number: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4, 8] + description: + Number of DOUTx lines used for the high-speed data output interface + (distinct from the SPI control interface). AD7768 supports 1, 2, or 8 + lines; AD7768-4 supports 1 or 4 lines. Defaults to the maximum number + of lines for the selected variant if omitted. + + regulators: + type: object + description: Container for the on-chip VCM regulator. + additionalProperties: false + + properties: + vcm-output: + type: object + description: + The VCM pin provides a buffered common-mode voltage output used to + bias the analog inputs. It supports three fixed output levels of + 1650000 uV, 2500000 uV, and 2140000 uV, as well as a + supply-dependent (AVDD1 - AVSS) / 2 output derived from + avdd1-supply. Select the voltage by setting regulator-min-microvolt + and regulator-max-microvolt to the same value. Use + regulator-always-on when no DT consumer node references the VCM + output. The VCM circuitry is associated with channel 0. When VCM is + used externally, channel@0 must be present and kept enabled because + placing channel 0 in standby disables the VCM output. + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + io-backends: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^channel@[0-7]$": + type: object + description: | + Represents the external channels which are connected to the device. + AD7768 supports channels 0-7, AD7768-4 supports channels 0-3. + + properties: + reg: + minimum: 0 + maximum: 7 + description: The channel number + + adi,prechargebuf-pos-enable: + type: boolean + description: Enable positive input precharge buffer + + adi,prechargebuf-neg-enable: + type: boolean + description: Enable negative input precharge buffer + + adi,refbuf-pos-enable: + type: boolean + description: Enable positive reference buffer + + adi,refbuf-neg-enable: + type: boolean + description: Enable negative reference buffer + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - avdd1-supply + - avss-supply + - avdd2-supply + - iovdd-supply + - ref1-supply + - ref2-supply + - io-backends + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + - if: + properties: + compatible: + contains: + const: adi,ad7768-4 + then: + properties: + adi,data-lines-number: + enum: [1, 4] + patternProperties: + "^channel@[0-3]$": + properties: + reg: + maximum: 3 + "^channel@[4-7]$": false + else: + properties: + adi,data-lines-number: + enum: [1, 2, 8] + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad7768"; + reg = <0>; + spi-max-frequency = <1000000>; + + avdd1-supply = <&avdd1_regulator>; + avss-supply = <&avss_regulator>; + avdd2-supply = <&avdd2_regulator>; + iovdd-supply = <&iovdd_regulator>; + ref1-supply = <&ref1_regulator>; + ref2-supply = <&ref2_regulator>; + reset-gpios = <&gpio0 86 GPIO_ACTIVE_LOW>; + + clocks = <&ad7768_mclk>; + + adi,data-lines-number = <8>; + gpio-controller; + #gpio-cells = <2>; + + io-backends = <&iio_backend>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + adi,prechargebuf-pos-enable; + adi,refbuf-pos-enable; + }; + + channel@1 { + reg = <1>; + adi,prechargebuf-pos-enable; + adi,prechargebuf-neg-enable; + adi,refbuf-pos-enable; + adi,refbuf-neg-enable; + }; + + channel@7 { + reg = <7>; + adi,prechargebuf-pos-enable; + adi,refbuf-pos-enable; + }; + }; + }; + + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@1 { + compatible = "adi,ad7768-4"; + reg = <1>; + spi-max-frequency = <1000000>; + + avdd1-supply = <&avdd1_regulator>; + avss-supply = <&avss_regulator>; + avdd2-supply = <&avdd2_regulator>; + iovdd-supply = <&iovdd_regulator>; + ref1-supply = <&ref1_regulator>; + ref2-supply = <&ref2_regulator>; + + clocks = <&ad7768_mclk>; + + adi,data-lines-number = <4>; + + io-backends = <&iio_backend>; + + #address-cells = <1>; + #size-cells = <0>; + + regulators { + vcm-output { + regulator-name = "vcm-output"; + regulator-min-microvolt = <2140000>; + regulator-max-microvolt = <2140000>; + regulator-always-on; + }; + }; + + channel@0 { + reg = <0>; + adi,prechargebuf-pos-enable; + adi,refbuf-pos-enable; + }; + + channel@3 { + reg = <3>; + adi,prechargebuf-pos-enable; + adi,refbuf-pos-enable; + }; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 2b1ec46c5919..d667a0411f28 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1633,6 +1633,13 @@ F: Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml F: drivers/iio/adc/ad7768-1.c F: include/dt-bindings/iio/adc/adi,ad7768-1.h +ANALOG DEVICES INC AD7768 DRIVER +M: Janani Sunil +L: linux-iio@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/adc/adi,ad7768.yaml + ANALOG DEVICES INC AD7780 DRIVER M: Michael Hennerich M: Renato Lui Geh -- 2.43.0