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Thu, 13 Aug 2026 02:38:28 -0700 From: To: , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , Subject: [PATCH v4 09/27] vfio/cxl: Create the CXL memory device at bind Date: Thu, 13 Aug 2026 15:06:13 +0530 Message-ID: <20260813093631.2288172-10-mhonap@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260813093631.2288172-1-mhonap@nvidia.com> References: <20260813093631.2288172-1-mhonap@nvidia.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000C6184:EE_|DM6PR12MB4252:EE_ X-MS-Office365-Filtering-Correlation-Id: 224942fc-2884-4678-d597-08def91eb177 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|36860700016|7416014|376014|1800799024|82310400026|921020|10067099003|11063799006|56012099006|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vOF3kkPgrRwrpfdcY9W055iBXiXI9qjo1a6+bKMzgwxA8LTUFMn+0rxsSEHj+imXC6CHAMtNmE3EqoUzSb542tUz/52hbSavT5Ou4wLk/hSckFX3I4hA9jpDlqg285oxDTnlg0EQPwxMup/H2e7WtCASckTfnw10g3PSGMPhM9Vm7FpLTewCOhlat3GYEzOTYYd1VxIhsQxOJKSICsFM6/r/bdRiJkXauZwa+PfeiQVZFFfYSXk5yN4hOhrttrTZwTOxlBfF611RO8TMGrGJHMUtCcKE/gr2VRdURK1OQ8cZqDEJhCyI6tXxDh4ijNthlWAnziuy19xszXb13TcCxWqTzs9N+pc0P9dgoNYHdksb7Hq5eEMV22crj7Jv6lpJ7crkxYNOL7ybLTOGja+wz+F+Fo/GLwFrNkqJSbwS3raWix8AVeuuJgm7ZfDK9cme X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2026 09:38:55.3397 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 224942fc-2884-4678-d597-08def91eb177 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000C6184.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4252 From: Manish Honap Read the HDM region size from decoder 0, cached in pdev->hdm at enumeration, and use it to size the accelerator device state. A Type-2 accelerator has no mailbox, so cxl_set_capacity() establishes the capacity that devm_cxl_probe_mem() then uses to join the device to the CXL topology and resolve the host physical range. Everything here is devm-scoped to the PCI device, so it is unwound when vfio-pci unbinds. If pdev->hdm is not populated yet, defer the bind. Signed-off-by: Manish Honap --- drivers/vfio/pci/cxl/vfio_cxl_core.c | 53 ++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/vfio/pci/cxl/vfio_cxl_core.c b/drivers/vfio/pci/cxl/vfio_cxl_core.c index cbec7319452c..125e11354a46 100644 --- a/drivers/vfio/pci/cxl/vfio_cxl_core.c +++ b/drivers/vfio/pci/cxl/vfio_cxl_core.c @@ -6,15 +6,67 @@ */ #include +#include +#include #include +#include + +/** + * struct vfio_cxl_state - per-device state for a vfio-cxl device + * @cxlds: CXL device state; kept first for devm_cxl_dev_state_create() + * @cxlmd: memory device joined to the CXL topology at bind + * @hpa_range: host physical range of the HDM region + */ +struct vfio_cxl_state { + struct cxl_dev_state cxlds; + struct cxl_memdev *cxlmd; + struct range hpa_range; +}; static int vfio_cxl_init_device(struct vfio_pci_core_device *vdev) { + struct pci_dev *pdev = vdev->pdev; + struct vfio_cxl_state *cxl; + struct cxl_memdev *cxlmd; + u64 hdm_size, serial; + u16 dvsec; + int ret; + + /* pdev->hdm is populated at PCI enumeration; defer until it is. */ + if (!pdev->hdm) + return -EPROBE_DEFER; + + hdm_size = range_len(&pdev->hdm->settings[0].hpa_range); + if (!hdm_size) + return -ENXIO; + + dvsec = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL, + PCI_DVSEC_CXL_DEVICE); + serial = pci_get_dsn(pdev); + + cxl = devm_cxl_dev_state_create(&pdev->dev, CXL_DEVTYPE_DEVMEM, serial, + dvsec, struct vfio_cxl_state, cxlds, + false); + if (!cxl) + return -ENOMEM; + + ret = cxl_set_capacity(&cxl->cxlds, hdm_size); + if (ret) + return ret; + + cxlmd = devm_cxl_probe_mem(&cxl->cxlds, &cxl->hpa_range); + if (IS_ERR(cxlmd)) + return PTR_ERR(cxlmd); + + cxl->cxlmd = cxlmd; + vdev->cxl = cxl; + return 0; } static void vfio_cxl_release_device(struct vfio_pci_core_device *vdev) { + vdev->cxl = NULL; } static const struct vfio_cxl_ops vfio_cxl_ops = { @@ -39,3 +91,4 @@ module_exit(vfio_cxl_exit); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("VFIO support for CXL Type-2 devices"); MODULE_ALIAS("vfio-cxl"); +MODULE_IMPORT_NS("CXL"); -- 2.25.1