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[79.26.252.140]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-49cdce08862sm51459635e9.1.2026.09.01.01.30.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 01:30:38 -0700 (PDT) From: Christian Marangi To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan , Randy Dunlap , Christian Marangi , Lorenzo Bianconi , Heiner Kallweit , Russell King , Philipp Zabel , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, llvm@lists.linux.dev Subject: [PATCH net-next v15 10/12] dt-bindings: net: pcs: Document support for Airoha Ethernet PCS Date: Tue, 1 Sep 2026 10:29:25 +0200 Message-ID: <20260901083001.8044-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901083001.8044-1-ansuelsmth@gmail.com> References: <20260901083001.8044-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Document support for Airoha Ethernet PCS for AN7581 SoC. Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for the various Serdes port supporting different Media Independent Interface (10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII). This follow the new PCS provider with the use of #pcs-cells property. Signed-off-by: Christian Marangi --- .../bindings/net/pcs/airoha,pcs.yaml | 261 ++++++++++++++++++ 1 file changed, 261 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml diff --git a/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml new file mode 100644 index 000000000000..9c1d116c1b01 --- /dev/null +++ b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml @@ -0,0 +1,261 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pcs/airoha,pcs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha Ethernet PCS and Serdes + +maintainers: + - Christian Marangi + +description: + Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for + the various Serdes port supporting different Media Independent Interface + (10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII). + +properties: + compatible: + enum: + - airoha,an7581-pcs-eth + - airoha,an7581-pcs-pon + - airoha,an7581-pcs-pcie + - airoha,an7581-pcs-usb + + reg: + minItems: 6 + maxItems: 15 + + reg-names: + minItems: 6 + maxItems: 15 + + airoha,scu: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the SCU node required to configure + the serdes line to the correct interface mode. + + phys: + maxItems: 1 + + "#pcs-cells": true + +required: + - compatible + - reg + - reg-names + - "#pcs-cells" + +allOf: + - if: + properties: + compatible: + contains: + enum: + - airoha,an7581-pcs-eth + - airoha,an7581-pcs-pon + + then: + properties: + reg: + items: + - description: PCS MAC reg + - description: HSGMII AN reg + - description: HSGMII PCS reg + - description: MULTI SGMII reg + - description: USXGMII reg + - description: HSGMII rate adaption reg + - description: PCS Analog register + - description: PCS PMA (Physical Medium Attachment) register + + reg-names: + items: + - const: pcs_mac + - const: hsgmii_an + - const: hsgmii_pcs + - const: multi_sgmii + - const: usxgmii + - const: hsgmii_rate_adp + - const: pcs_ana + - const: pcs_pma + + phys: false + + "#pcs-cells": + const: 0 + + required: + - airoha,scu + + - if: + properties: + compatible: + contains: + const: airoha,an7581-pcs-pcie + + then: + properties: + reg: + items: + - description: PCS MAC 0 reg + - description: HSGMII AN 0 reg + - description: HSGMII PCS 0 reg + - description: MULTI SGMII 0 reg + - description: USXGMII 0 reg + - description: HSGMII rate adaption 0 reg + - description: PCS MAC 1 reg + - description: HSGMII AN 1 reg + - description: HSGMII PCS 1 reg + - description: MULTI SGMII 1 reg + - description: USXGMII 1 reg + - description: HSGMII rate adaption 1 reg + - description: PCS Analog register + - description: PCS PMA (Physical Medium Attachment) 0 register + - description: PCS PMA (Physical Medium Attachment) 1 register + + reg-names: + items: + - const: pcs_mac0 + - const: hsgmii_an0 + - const: hsgmii_pcs0 + - const: multi_sgmii0 + - const: usxgmii0 + - const: hsgmii_rate_adp0 + - const: pcs_mac1 + - const: hsgmii_an1 + - const: hsgmii_pcs1 + - const: multi_sgmii1 + - const: usxgmii1 + - const: hsgmii_rate_adp1 + - const: pcs_ana + - const: pcs_pma0 + - const: pcs_pma1 + + phys: false + + "#pcs-cells": + const: 1 + + required: + - airoha,scu + + - if: + properties: + compatible: + contains: + const: airoha,an7581-pcs-usb + + then: + properties: + reg: + items: + - description: PCS MAC reg + - description: HSGMII AN reg + - description: HSGMII PCS reg + - description: MULTI SGMII reg + - description: HSGMII rate adaption reg + - description: PCS Analog register + + reg-names: + items: + - const: pcs_mac + - const: hsgmii_an + - const: hsgmii_pcs + - const: multi_sgmii + - const: hsgmii_rate_adp + - const: pcs_ana + + airoha,scu: false + + "#pcs-cells": + const: 0 + + required: + - phys + +additionalProperties: false + +examples: + - | + #include + + pcs@1fa08000 { + compatible = "airoha,an7581-pcs-pon"; + reg = <0x1fa08000 0x1000>, + <0x1fa80000 0x60>, + <0x1fa80a00 0x164>, + <0x1fa84000 0x450>, + <0x1fa85900 0x338>, + <0x1fa86000 0x300>, + <0x1fa8a000 0x1000>, + <0x1fa8b000 0x1000>; + reg-names = "pcs_mac", "hsgmii_an", "hsgmii_pcs", + "multi_sgmii", "usxgmii", + "hsgmii_rate_adp", "pcs_ana", "pcs_pma"; + + airoha,scu = <&scuclk>; + #pcs-cells = <0>; + }; + + pcs@1fa09000 { + compatible = "airoha,an7581-pcs-eth"; + reg = <0x1fa09000 0x1000>, + <0x1fa70000 0x60>, + <0x1fa70a00 0x164>, + <0x1fa74000 0x450>, + <0x1fa75900 0x338>, + <0x1fa76000 0x300>, + <0x1fa7a000 0x1000>, + <0x1fa7b000 0x1000>; + reg-names = "pcs_mac", "hsgmii_an", "hsgmii_pcs", + "multi_sgmii", "usxgmii", + "hsgmii_rate_adp", "pcs_ana", "pcs_pma"; + + airoha,scu = <&scuclk>; + #pcs-cells = <0>; + }; + + pcs@1fa04000 { + compatible = "airoha,an7581-pcs-pcie"; + reg = <0x1fa04000 0x1000>, + <0x1fa50000 0x60>, + <0x1fa50a00 0x164>, + <0x1fa54000 0x450>, + <0x1fa55900 0x338>, + <0x1fa56000 0x300>, + <0x1fa05000 0x1000>, + <0x1fa60000 0x60>, + <0x1fa60a00 0x164>, + <0x1fa64000 0x450>, + <0x1fa65900 0x338>, + <0x1fa66000 0x300>, + <0x1fa5a000 0x1000>, + <0x1fa5b000 0x1000>, + <0x1fa5c000 0x1000>; + reg-names = "pcs_mac0", "hsgmii_an0", "hsgmii_pcs0", + "multi_sgmii0", "usxgmii0", + "hsgmii_rate_adp0", + "pcs_mac1", "hsgmii_an1", "hsgmii_pcs1", + "multi_sgmii1", "usxgmii1", + "hsgmii_rate_adp1", + "pcs_ana", "pcs_pma0", "pcs_pma1"; + + airoha,scu = <&scuclk>; + #pcs-cells = <1>; + }; + + pcs@1fa07000 { + compatible = "airoha,an7581-pcs-usb"; + reg = <0x1fa07000 0x1000>, + <0x1fa90000 0x60>, + <0x1fa90a00 0x164>, + <0x1fa94000 0x450>, + <0x1fa96000 0x300>, + <0x1fa9a000 0x600>; + reg-names = "pcs_mac", "hsgmii_an", "hsgmii_pcs", + "multi_sgmii", "hsgmii_rate_adp","pcs_ana"; + + phys = <&usb0_phy PHY_TYPE_USB3>; + + #pcs-cells = <0>; + }; -- 2.53.0