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Derive the delay resolution from MCLK, power mode and decimation rate. Validate the requested delay and program the corresponding phase register when applying the active channel configuration. Signed-off-by: Janani Sunil --- drivers/iio/adc/ad7768.c | 136 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c index e9462278a812..be2eb21c5b63 100644 --- a/drivers/iio/adc/ad7768.c +++ b/drivers/iio/adc/ad7768.c @@ -146,6 +146,12 @@ struct ad7768_freq_config { unsigned int dec_rate; }; +struct ad7768_convdelay_params { + unsigned int shift; + unsigned int max_raw; + u64 step_ps; +}; + struct ad7768_avail_freq { unsigned int n_freqs; struct ad7768_freq_config freq_cfg[AD7768_MAX_FREQ_PER_MODE]; @@ -172,6 +178,7 @@ struct ad7768_state { struct ad7768_avail_freq avail_freq[ARRAY_SIZE(ad7768_power_modes)]; unsigned int n_freqs; int freqs[AD7768_MAX_FREQS]; + u64 ch_convdelay_ps[AD7768_MAX_CHANNEL]; unsigned int ch_freq[AD7768_MAX_CHANNEL]; unsigned int power_mode_idx; enum ad7768_filter_type ch_filter[AD7768_MAX_CHANNEL]; @@ -261,6 +268,12 @@ static unsigned int ad7768_gain_reg(const struct ad7768_state *st, return AD7768_REG_GAIN(st->chip_info->chan_map[ch]); } +static unsigned int ad7768_phase_reg(const struct ad7768_state *st, + unsigned int ch) +{ + return AD7768_REG_PHASE(st->chip_info->chan_map[ch]); +} + static u8 ad7768_precharge_buf1_mask(const struct ad7768_state *st, u16 val) { return val & GENMASK(st->chip_info->prebuf_split - 1, 0); @@ -699,6 +712,99 @@ static int ad7768_find_matching_mode(const bool *mode_used, return -EINVAL; } +static int ad7768_get_convdelay_params(struct ad7768_state *st, unsigned int ch, + struct ad7768_convdelay_params *params) +{ + const struct ad7768_freq_config *freq_cfg; + unsigned int dec_rate; + unsigned int mclk_div; + unsigned long mclk; + u64 mult; + + freq_cfg = ad7768_find_freq_config(st, st->power_mode_idx, + st->ch_freq[ch]); + if (!freq_cfg) + return -EINVAL; + + dec_rate = ad7768_dec_rate[freq_cfg->dec_rate]; + switch (dec_rate) { + case 32: + params->shift = 3; + params->max_raw = 31; + mult = 1; + break; + case 64: + params->shift = 2; + params->max_raw = 63; + mult = 1; + break; + case 128: + params->shift = 1; + params->max_raw = 127; + mult = 1; + break; + case 256: + params->shift = 0; + params->max_raw = 255; + mult = 1; + break; + case 512: + params->shift = 0; + params->max_raw = 255; + mult = 2; + break; + case 1024: + params->shift = 0; + params->max_raw = 255; + mult = 4; + break; + default: + return -EINVAL; + } + + mclk = clk_get_rate(st->mclk); + if (!mclk || mclk > U32_MAX) + return -EINVAL; + + mclk_div = ad7768_power_modes[st->power_mode_idx].mclk_div; + params->step_ps = + DIV_ROUND_CLOSEST_ULL(mult * PSEC_PER_SEC * mclk_div, (u32)mclk); + if (params->step_ps > U32_MAX) + return -EINVAL; + + return 0; +} + +static int ad7768_set_channel_convdelay(struct ad7768_state *st, + unsigned int ch) +{ + u64 delay_ps = st->ch_convdelay_ps[ch]; + struct ad7768_convdelay_params params; + u64 max_delay_ps; + u64 raw; + int ret; + + ret = ad7768_get_convdelay_params(st, ch, ¶ms); + if (ret) + return ret; + + /* + * Validate the requested delay before rounding so an out-of-range value + * cannot round down into the valid range. Then verify that the rounded + * value fits in the hardware register. + */ + max_delay_ps = (u64)params.max_raw * params.step_ps; + if (delay_ps > max_delay_ps) + return -EINVAL; + + raw = DIV_ROUND_CLOSEST_ULL(delay_ps, (u32)params.step_ps); + if (raw > params.max_raw) + return -EINVAL; + + return regmap_write(st->regmap, ad7768_phase_reg(st, ch), + raw << params.shift); +} + static void ad7768_filter_wait(const unsigned int *mode_freq, const enum ad7768_filter_type *mode_filter, const bool *mode_used) @@ -799,6 +905,16 @@ static int ad7768_apply_channel_modes(struct iio_dev *indio_dev, max_freq = max(max_freq, mode_freq[mode]); } + for_each_set_bit(c, scan_mask, st->chip_info->num_channels) { + ret = ad7768_set_channel_convdelay(st, c); + if (ret == -EINVAL) + return dev_err_probe(regmap_get_device(st->regmap), ret, + "Invalid conversion delay for channel %u\n", + c); + if (ret) + return ret; + } + ret = ad7768_set_clk_divs(st, max_freq); if (ret) return ret; @@ -918,6 +1034,13 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, return IIO_VAL_INT; } + case IIO_CHAN_INFO_CONVDELAY: { + guard(mutex)(&st->lock); + iio_val_s64_decompose(st->ch_convdelay_ps[chan->channel], + val, val2); + + return IIO_VAL_DECIMAL64_PICO; + } default: return -EINVAL; } @@ -931,6 +1054,8 @@ static int ad7768_write_raw_get_fmt(struct iio_dev *indio_dev, case IIO_CHAN_INFO_CALIBBIAS: case IIO_CHAN_INFO_CALIBSCALE: return IIO_VAL_INT; + case IIO_CHAN_INFO_CONVDELAY: + return IIO_VAL_DECIMAL64_PICO; default: return -EINVAL; } @@ -942,6 +1067,7 @@ static int ad7768_write_raw(struct iio_dev *indio_dev, { struct ad7768_state *st = iio_priv(indio_dev); unsigned int base_reg; + s64 delay_ps; IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); if (IIO_DEV_ACQUIRE_FAILED(claim)) @@ -956,6 +1082,15 @@ static int ad7768_write_raw(struct iio_dev *indio_dev, case IIO_CHAN_INFO_CALIBSCALE: base_reg = ad7768_get_calib_reg_base(st, chan, true); return ad7768_write_calib_value(st, base_reg, false, val); + case IIO_CHAN_INFO_CONVDELAY: { + delay_ps = iio_val_s64_compose(val, val2); + if (delay_ps < 0) + return -EINVAL; + + guard(mutex)(&st->lock); + st->ch_convdelay_ps[chan->channel] = delay_ps; + return 0; + } default: return -EINVAL; } @@ -1162,6 +1297,7 @@ static int ad7768_parse_config(struct iio_dev *indio_dev, .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT(IIO_CHAN_INFO_CALIBSCALE) | + BIT(IIO_CHAN_INFO_CONVDELAY) | BIT(IIO_CHAN_INFO_SAMP_FREQ), .info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), -- 2.43.0