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Replace the fixed x64 decimation with the derived default output rate and a new decimation helper. Extend the existing clock-divider helper to derive the DCLK divider from the selected rate. Select the maximum rate supported by the configured data interface for the initial capture configuration. Signed-off-by: Janani Sunil --- drivers/iio/adc/ad7768.c | 134 ++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 115 insertions(+), 19 deletions(-) diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c index 5bd01f457a54..2d051d91e1cf 100644 --- a/drivers/iio/adc/ad7768.c +++ b/drivers/iio/adc/ad7768.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -34,7 +35,6 @@ #define AD7768_CH_MODE_FILTER_TYPE_MSK BIT(3) #define AD7768_CH_MODE_FILTER_TYPE_WIDEBAND 0x0 #define AD7768_CH_MODE_DEC_RATE_MSK GENMASK(2, 0) -#define AD7768_CH_MODE_DEC_RATE_64 0x1 #define AD7768_REG_CH_MODE_SEL 0x03 @@ -93,9 +93,12 @@ #define AD7768_SPI_REG_MASK GENMASK(14, 8) #define AD7768_SPI_DATA_MASK GENMASK(7, 0) +#define AD7768_SAMPLE_SIZE 32 +#define AD7768_MAX_DCLK_DIV 8 #define AD7768_MIN_MCLK_FREQ_HZ (1150 * HZ_PER_KHZ) #define AD7768_MIN_XTAL_FREQ_HZ (8 * HZ_PER_MHZ) #define AD7768_MAX_MCLK_FREQ_HZ (34 * HZ_PER_MHZ) +#define AD7768_MAX_FREQ_PER_MODE 6 #define AD7768_MAX_CHANNEL 8 enum ad7768_clock_source { @@ -122,6 +125,16 @@ struct ad7768_precharge_config { bool refbufn; }; +struct ad7768_freq_config { + unsigned int freq_hz; + unsigned int dec_rate; +}; + +struct ad7768_avail_freq { + unsigned int n_freqs; + struct ad7768_freq_config freq_cfg[AD7768_MAX_FREQ_PER_MODE]; +}; + struct ad7768_chip_info { const char *name; const struct regmap_config *regmap_config; @@ -138,6 +151,8 @@ struct ad7768_state { unsigned int datalines; enum ad7768_clock_source clock_source; const struct ad7768_chip_info *chip_info; + struct ad7768_avail_freq avail_freq[ARRAY_SIZE(ad7768_power_modes)]; + unsigned int ch_freq[AD7768_MAX_CHANNEL]; struct iio_backend *back; unsigned int vref_uV[2]; unsigned int power_mode_idx; @@ -146,6 +161,10 @@ struct ad7768_state { __be16 d16 __aligned(IIO_DMA_MINALIGN); }; +static const unsigned int ad7768_dec_rate[AD7768_MAX_FREQ_PER_MODE] = { + 32, 64, 128, 256, 512, 1024, +}; + static const unsigned int ad7768_available_datalines[] = { 1, 2, 8, }; @@ -386,17 +405,45 @@ static int ad7768_set_power_mode(struct ad7768_state *st, return 0; } -static int ad7768_set_clk_divs(struct ad7768_state *st) +static const struct ad7768_freq_config * +ad7768_find_freq_config(const struct ad7768_state *st, + unsigned int mode_idx, unsigned int freq) { + const struct ad7768_avail_freq *avail_freq = &st->avail_freq[mode_idx]; + + for (unsigned int i = 0; i < avail_freq->n_freqs; i++) { + if (freq == avail_freq->freq_cfg[i].freq_hz) + return &avail_freq->freq_cfg[i]; + } + + return NULL; +} + +static int ad7768_set_clk_divs(struct ad7768_state *st, unsigned int freq) +{ + const struct ad7768_freq_config *freq_cfg; + unsigned int mclk, dclk, dclk_div; + unsigned int chan_per_doutx; unsigned int dclk_div_reg; - unsigned int dclk_div; - /* - * DCLK(min) is ODR * channels per DOUTx * 32. With fast mode - * (fMOD = MCLK / 4) and x64 decimation, this gives: - * MCLK / DCLK = 8 * data lines / channels. - */ - dclk_div = 8 * st->datalines / st->chip_info->num_channels; + freq_cfg = ad7768_find_freq_config(st, st->power_mode_idx, freq); + if (!freq_cfg) + return -EINVAL; + + mclk = clk_get_rate(st->mclk); + chan_per_doutx = st->chip_info->num_channels / st->datalines; + if (!chan_per_doutx) + return -EINVAL; + + dclk = freq_cfg->freq_hz * AD7768_SAMPLE_SIZE * chan_per_doutx; + if (dclk > mclk) + return -EINVAL; + + dclk_div = DIV_ROUND_CLOSEST(mclk, dclk); + + /* Set the divider to the next-lowest supported power of two. */ + dclk_div = rounddown_pow_of_two(min(dclk_div, AD7768_MAX_DCLK_DIV)); + switch (dclk_div) { case 1: dclk_div_reg = AD7768_INTERFACE_CFG_DCLK_DIV_1; @@ -420,6 +467,21 @@ static int ad7768_set_clk_divs(struct ad7768_state *st) dclk_div_reg)); } +static int ad7768_set_mode_decimation(struct ad7768_state *st, + unsigned int freq, unsigned int mode) +{ + const struct ad7768_freq_config *freq_cfg; + + freq_cfg = ad7768_find_freq_config(st, st->power_mode_idx, freq); + if (!freq_cfg) + return -EINVAL; + + return regmap_update_bits(st->regmap, AD7768_REG_CH_MODE(mode), + AD7768_CH_MODE_DEC_RATE_MSK, + FIELD_PREP(AD7768_CH_MODE_DEC_RATE_MSK, + freq_cfg->dec_rate)); +} + static int ad7768_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask) { @@ -567,8 +629,37 @@ static int ad7768_configure_precharge_buffers(struct iio_dev *indio_dev, return regmap_write(st->regmap, AD7768_REG_REFN_BUF, refbufn_val); } +static void ad7768_set_available_sampling_freqs(struct ad7768_state *st) +{ + unsigned int n_power_modes = ARRAY_SIZE(ad7768_power_modes); + unsigned int mclk = clk_get_rate(st->mclk); + + for (unsigned int mode_idx = 0; mode_idx < n_power_modes; mode_idx++) { + unsigned int dec = ARRAY_SIZE(ad7768_dec_rate); + struct ad7768_avail_freq *avail_freq; + unsigned int div; + + avail_freq = &st->avail_freq[mode_idx]; + div = ad7768_power_modes[mode_idx].mclk_div; + while (dec--) { + struct ad7768_freq_config *freq_cfg; + + freq_cfg = &avail_freq->freq_cfg[avail_freq->n_freqs++]; + freq_cfg->dec_rate = dec; + freq_cfg->freq_hz = mclk / (ad7768_dec_rate[dec] * div); + } + } + + /* One DOUT line cannot carry the AD7768 fast-mode x32 output rate. */ + if (st->datalines == 1 && + st->chip_info->num_channels == AD7768_MAX_CHANNEL) + st->avail_freq[n_power_modes - 1].n_freqs--; +} + static int ad7768_configure_capture(struct ad7768_state *st) { + const struct ad7768_avail_freq *avail_freq; + unsigned int default_freq; unsigned int mode_config; int ret; @@ -576,17 +667,20 @@ static int ad7768_configure_capture(struct ad7768_state *st) if (ret) return ret; - /* - * Start with the wideband filter and a decimation rate of 64. This - * supports every valid data-line configuration at the maximum MCLK. - */ + avail_freq = &st->avail_freq[st->power_mode_idx]; + default_freq = avail_freq->freq_cfg[avail_freq->n_freqs - 1].freq_hz; + for (unsigned int channel = 0; + channel < st->chip_info->num_channels; channel++) + st->ch_freq[channel] = default_freq; + + ret = ad7768_set_mode_decimation(st, default_freq, 0); + if (ret) + return ret; + mode_config = FIELD_PREP(AD7768_CH_MODE_FILTER_TYPE_MSK, - AD7768_CH_MODE_FILTER_TYPE_WIDEBAND) | - FIELD_PREP(AD7768_CH_MODE_DEC_RATE_MSK, - AD7768_CH_MODE_DEC_RATE_64); + AD7768_CH_MODE_FILTER_TYPE_WIDEBAND); ret = regmap_update_bits(st->regmap, AD7768_REG_CH_MODE(0), - AD7768_CH_MODE_FILTER_TYPE_MSK | - AD7768_CH_MODE_DEC_RATE_MSK, + AD7768_CH_MODE_FILTER_TYPE_MSK, mode_config); if (ret) return ret; @@ -595,7 +689,7 @@ static int ad7768_configure_capture(struct ad7768_state *st) if (ret) return ret; - ret = ad7768_set_clk_divs(st); + ret = ad7768_set_clk_divs(st, default_freq); if (ret) return ret; @@ -707,6 +801,8 @@ static int ad7768_parse_config(struct iio_dev *indio_dev, "Invalid %s %u for %s\n", propname, st->datalines, st->chip_info->name); + ad7768_set_available_sampling_freqs(st); + return ad7768_configure_capture(st); } -- 2.43.0