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[83.233.130.25]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae6dcf0dsm197647666b.61.2026.09.23.14.59.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 14:59:12 -0700 (PDT) From: Yongzhao Chen To: netdev@vger.kernel.org Cc: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Jonathan Corbet , Shuah Khan , Randy Dunlap , Florian Fainelli , Jonas Gorski , Andrew Lunn , Vladimir Oltean , Woojung Huh , UNGLinuxDriver@microchip.com, Christian Marangi , Heiner Kallweit , Russell King , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Ziyang Huang Subject: [RFC PATCH net-next v3 0/5] net: dsa: qca8k: add a QCA8337 CPU PHY consumer Date: Wed, 23 Sep 2026 23:58:52 +0200 Message-ID: <20260923215858.1653-1-yongzhao.derek@gmail.com> X-Mailer: git-send-email 2.45.2.windows.1 Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The qca83xx PHY driver is already in net-next. This series allows passing PHY flags on DSA shared ports and adds support for a QCA8337 internal CPU PHY. It implements CPU port selection, serializes MAC state across global MTU updates, and proposes disabling SmartSpeed prior to CPU PHY resets. The first patch extends the DSA core interface; the qca8k patches provide its concrete user. No board-name matching or board-specific DT properties are introduced. The minimal topology uses a single CPU link: a conduit PHY connects over MDI to QCA8337 PHY4 on switch port 5, with each endpoint having its own phy-handle. A reduced devicetree fixture based on Redmi AX5400 wiring passed dtc and validation against the complete net-next schema set. This is a binding fixture rather than a bootable board description. Because the pinned base tree lacks the IPQ5018 Ethernet MAC driver and RA74 board support, this series has not been boot-tested on RA74 under pure net-next. On one RA74 board, diagnostic boot logs showed PHY4 advertising 1000BASE-T full duplex after generic config_aneg() succeeded, but a later read found the advertisement missing. No intervening write was found through the instrumented Clause 22 BMCR/CTRL1000 path; other paths were not excluded. The exact trigger remains unknown. Clearing SmartSpeed before the initial reset preserved the 1 Gb/s internal link during the tested boot sequence. Runtime testing did not establish late-peer causality, a broken pair, or successful fallback to 100 Mb/s. Two scope questions remain for this RFC: 1. Internal CPU port selection currently falls back to ports 1 through 5 only on QCA8337. Dedicated ports 0 and 6 retain priority on all models, including mixed CPU port descriptions. AR8327 documentation describes per-port headers and destination bitmaps, but I have not established its internal CPU link behavior. Should this fallback remain limited to QCA8337, or can maintainers confirm the same support for QCA8327? 2. The proposed SmartSpeed policy applies to QCA8337 internal CPU PHYs. SmartSpeed is the hardware downshift feature, so disabling it removes that fallback behavior. Current hardware evidence is limited to PHY4 on a single RA74 board. Is the internal CPU link role sufficient justification for this policy, or should the quirk be scoped more narrowly? Changes since v2: - Patch 2 uses reg_mutex across the MTU pause, frame-size write, and state restoration. Variable declarations now follow reverse Christmas-tree order. This patch precedes topology support so MTU protection is in place when internal CPU ports become available. - Patch 3 adds internal CPU port fallback while retaining port 0 and 6 priority, leaving QCA8327 support as an explicit RFC question. - Patch 4 masks the revision before setting the CPU PHY flag, clarifies SmartSpeed downshift behavior, and drops the delayed-conduit causal claim. - Patch 5 clarifies reset and config_aneg ordering along with hardware evidence limits, keeping generic config_aneg. This series depends on the separate net patch "net: dsa: qca8k: propagate MDIO errors": https://lore.kernel.org/netdev/20260923215748.1336-1-yongzhao.derek@gmail.com/ Testing: Fault injection against the actual MDIO/PHY functions and kernel polling macros covered busy-read errors, timeouts and successful transactions. The old polling code reproduced false success on read error; the fixed path blocked SmartSpeed writes and initial/resume resets. Tests with mocked hardware also covered flag scope, CPU-port selection and MDIO-to-MTU error handling. The changed qca8k-8xxx.o built with W=1 for x86_64 and ARM64 under allyesconfig and allmodconfig, with no compiler diagnostics. Unchanged qca8k-common.o and MTU locking retain the earlier build and concurrency test results. Hardware tests used downstream RA74 firmware. This revision has no full kernel image/modules build, pure net-next RA74 boot or hardware lockdep run. Original RFC: https://lore.kernel.org/netdev/20260919085406.1395-1-yongzhao.derek@gmail.com/ v2: https://lore.kernel.org/netdev/20260922202653.1153-1-yongzhao.derek@gmail.com/ Base: net-next 8830e65ed46de41f849eefb8ba227d4852c460f6. Local prerequisite: 3ba847ea54227f704ee3b04f95d4b52d4e22d483. Yongzhao Chen (4): net: dsa: pass PHY flags when connecting shared ports net: dsa: qca8k: serialize CPU MAC pause during MTU changes net: dsa: qca8k: flag QCA8337 internal CPU PHYs for SmartSpeed net: phy: qca83xx: disable SmartSpeed before resetting CPU PHYs Ziyang Huang (1): net: dsa: qca8k: support QCA8337 internal PHY CPU links Documentation/networking/dsa/dsa.rst | 2 + MAINTAINERS | 1 + drivers/net/dsa/bcm_sf2.c | 4 ++ drivers/net/dsa/microchip/ksz8.c | 4 ++ drivers/net/dsa/qca/qca8k-8xxx.c | 39 +++++++++----- drivers/net/dsa/qca/qca8k-common.c | 79 ++++++++++++++++++++++------ drivers/net/phy/qcom/qca83xx.c | 32 +++++++++-- include/linux/qca83xx.h | 11 ++++ net/dsa/port.c | 6 ++- 9 files changed, 145 insertions(+), 33 deletions(-) create mode 100644 include/linux/qca83xx.h -- 2.43.0