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Fri, 16 Oct 2026 09:21:53 -0700 From: To: , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , Subject: [PATCH v6 20/31] vfio/cxl: Own the whole component register BAR Date: Fri, 16 Oct 2026 21:48:27 +0530 Message-ID: <20261016161839.2765592-21-mhonap@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261016161839.2765592-1-mhonap@nvidia.com> References: <20261016161839.2765592-1-mhonap@nvidia.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH01EPF000BE94D:EE_|LY0PR12MB461782:EE_ X-MS-Office365-Filtering-Correlation-Id: 63375de8-24f3-48f5-586b-08df2ba1aa88 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|36860700016|23010399003|82310400026|56012099006|11063799006|261009223027099003|921020|10067099003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: uxTzKrkKexqTjcpluaS4O1EqO+zO9Hj20q2d1L+/3V76zdcL3nHiSpPyhE/oHYCmyGNc0B0kuSRbyo29V9PAGgOxYZXJi6873Hw/bKoMdq5EZW1dNBsHpA0lHz9TYD8/qITBzT/HTpF3RgnhyJBjNT+5Vm6c8ZXjnYrRgmIPqHiOl6jTsyBy8VSnWJBYkpxZlUkJE4MSAVQAnlc633n9phuOPtFg7zJbT3J3IuWwOKNbhU36yQkVyi8Evd5sNjyTqqLu3AmuZXPXzBQHy4Sa2VueNxuOhi7qHJjHU8uOP/ADEHRlAq5ONSP7uhvxyAIMImQUWs/wWatadgHQE4dMlV2ZBmfxpS6vesSzwejNxjQnzjr9kOIJz1Vg5GsUwL+QWKTgDBfPwmvDNVxpB9XQAtVffClDwEv55DwuA+XVYhuLvPADMG5/5YoBjcfNkZzX X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2026 16:22:25.9054 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 63375de8-24f3-48f5-586b-08df2ba1aa88 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH01EPF000BE94D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LY0PR12MB461782 From: Manish Honap devm_cxl_probe_mem() maps the component registers through the CXL core, which by default claims each HDM and RAS sub-block. That collides with the full-BAR request vfio-pci-core makes when the guest opens the device. After the component registers are discovered, declare the containing BAR owned with cxl_reg_map_set_owned_resource(). The core then ioremaps the sub-blocks without requesting them, so vfio-pci-core owns the whole BAR and the requests do not collide. Assisted-by: LLM Signed-off-by: Manish Honap --- drivers/vfio/pci/cxl/vfio_cxl_core.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/vfio/pci/cxl/vfio_cxl_core.c b/drivers/vfio/pci/cxl/vfio_cxl_core.c index ef1fc715020e..052be27bc46f 100644 --- a/drivers/vfio/pci/cxl/vfio_cxl_core.c +++ b/drivers/vfio/pci/cxl/vfio_cxl_core.c @@ -33,8 +33,9 @@ struct vfio_cxl_state { * Create the CXL device state and join the device to the CXL topology. The * caller groups these devres allocations, so return on the first error. */ -static struct vfio_cxl_state *vfio_cxl_create_memdev(struct pci_dev *pdev, - u64 hdm_size) +static struct vfio_cxl_state * +vfio_cxl_create_memdev(struct pci_dev *pdev, const struct cxl_hdm_info *hdm, + u64 hdm_size) { struct vfio_cxl_state *cxl; struct cxl_memdev *cxlmd; @@ -59,6 +60,17 @@ static struct vfio_cxl_state *vfio_cxl_create_memdev(struct pci_dev *pdev, return ERR_PTR(ret); } + /* + * vfio-pci-core requests the whole component-register BAR when the + * guest opens the device. Declare that BAR owned so the CXL core + * ioremaps the HDM and RAS sub-blocks without claiming them, and the + * full-BAR request does not collide. + */ + ret = cxl_reg_map_set_owned_resource(&cxl->cxlds.reg_map, + pci_resource_n(pdev, hdm->hdm_bar)); + if (ret) + return ERR_PTR(ret); + if (!cxl->cxlds.reg_map.component_map.hdm_decoder.valid) { pci_err(pdev, "vfio-cxl: HDM decoder registers not found\n"); return ERR_PTR(-ENODEV); @@ -133,7 +145,7 @@ static int vfio_cxl_init_device(struct vfio_pci_core_device *vdev) if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) return -ENOMEM; - cxl = vfio_cxl_create_memdev(pdev, hdm_size); + cxl = vfio_cxl_create_memdev(pdev, hdm, hdm_size); if (IS_ERR(cxl)) { devres_release_group(&pdev->dev, NULL); return PTR_ERR(cxl); -- 2.53.0