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Fri, 16 Oct 2026 09:22:37 -0700 From: To: , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , Subject: [PATCH v6 25/31] vfio/cxl: Exclude the HDM decoder registers from direct BAR access Date: Fri, 16 Oct 2026 21:48:32 +0530 Message-ID: <20261016161839.2765592-26-mhonap@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261016161839.2765592-1-mhonap@nvidia.com> References: <20261016161839.2765592-1-mhonap@nvidia.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH01EPF000BE94E:EE_|DS0PR12MB9321:EE_ X-MS-Office365-Filtering-Correlation-Id: 33b7d5cc-5dcb-4f0d-b45f-08df2ba1c4be X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|23010399003|1800799024|7416014|376014|18002099003|22082099003|10067099003|921020|261009223027099003|11063799006|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: aintD0yG69kpYxw+SGNazxqfG8xKuzOk8aBPmMxECl/GzsOrsM8hLNWu5vOD6GWXL9VFacWg1bOoyS4ikbn6g52gamcta+JSzmclVnUD/UynmGOBZEoQLYmKMWgXEINA7PL0C/+i+HHxmkrGE3dRPJ22f3FabIBzo2jjlOfZstndO56+XOXXsN/4nztznsO7Do8kr+UXNwbriOhaMcbNDy678ur3C5KjcRuRAwky2phSZIJpSOEHEFs7ajr0DEUJQI2+CJO/p3Rt3smmJ69+jyHyMhTgWegzX1i0gNGZ0JNd19xltH7nEtY6Sxux51JXtPdhvKyaU9jctVEJOKN3ZOCA3uFPOR5JtHTSNxDK7+T8gGdC8cPQpZ3ru3Pi33l8Zjfw/Gx79YCQEQOy5SRyifD6Gb0sPcrCYHqdZoRgY7M3IFBqgrckEXpglrX5lN2R X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2026 16:23:09.8913 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 33b7d5cc-5dcb-4f0d-b45f-08df2ba1c4be X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH01EPF000BE94E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9321 From: Manish Honap The HDM decoder register block lives in the component BAR that vfio-pci owns. The guest reads the decoder only through the trapped, read-only decoder region; it must not reach the physical registers through the BAR directly, and a write through the BAR could uncommit or move an unlocked decoder that the host relies on. Add the block to the generic excluded-range list with VFIO_PCI_EXCLUDE_MMAP | VFIO_PCI_EXCLUDE_READ | VFIO_PCI_EXCLUDE_WRITE similar to the MSI-X exclusion. Assisted-by: LLM Signed-off-by: Manish Honap --- drivers/vfio/pci/cxl/vfio_cxl_core.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/vfio/pci/cxl/vfio_cxl_core.c b/drivers/vfio/pci/cxl/vfio_cxl_core.c index 4a8aaa765a98..68e898ee1985 100644 --- a/drivers/vfio/pci/cxl/vfio_cxl_core.c +++ b/drivers/vfio/pci/cxl/vfio_cxl_core.c @@ -614,6 +614,22 @@ static int vfio_cxl_open_device(struct vfio_pci_core_device *vdev) struct vfio_cxl_state *cxl = vdev->cxl; int ret; + /* + * Keep the HDM decoder block out of the guest's direct BAR access: the + * guest reaches it only through the trapped decoder region, and a write + * through the BAR could uncommit or move an unlocked decoder that the + * host relies on. Exclude it from mmap, fill reads with -1 and drop + * writes. The list is cleared on close, so re-add it per open. + */ + ret = vfio_pci_core_add_excluded_range(vdev, cxl->hdm->hdm_bar, + cxl->hdm->hdm_offset, + cxl->hdm_len, + VFIO_PCI_EXCLUDE_MMAP | + VFIO_PCI_EXCLUDE_READ | + VFIO_PCI_EXCLUDE_WRITE); + if (ret) + return ret; + /* * vfio-pci-core frees all dynamic regions on close and on a failed * open, so register them here per open rather than at bind. -- 2.53.0