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Fri, 16 Oct 2026 09:19:49 -0700 From: To: , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , Subject: [PATCH v6 06/31] vfio/pci: Add the CXL provider ops registration interface Date: Fri, 16 Oct 2026 21:48:13 +0530 Message-ID: <20261016161839.2765592-7-mhonap@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261016161839.2765592-1-mhonap@nvidia.com> References: <20261016161839.2765592-1-mhonap@nvidia.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH01EPF000BE949:EE_|IA1PR12MB6356:EE_ X-MS-Office365-Filtering-Correlation-Id: d3c3fa98-1032-4c66-8e9b-08df2ba1615e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|23010399003|7416014|82310400026|36860700016|56012099006|921020|11063799006|261009223027099003|10067099003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: OSBjIDDlGAIq6IlKPuVBlvAMDlZVUeV6WkvFl2q73uYrBv1WQ2E8raQFN3+ur+zKs/sshvK3XNXPZSWyf4ky280stBNvGaFKkgskEdNQwxofpWhBIjl2cEnSlbfS6QAEjAIAkCI5AxOZQzC2MJVhNdTyOBwdH/eDX0OewQvimPVjP053eLjjFSAmTQLKJKvocKlPmALLavcm8PmH58CANZaPMT3zaUjhXYYXzxAgFqL3gMLobNsKht0iXqGz/M9ze6kCHDN3wRyat4LwUMSQAmd1c67MAuRSFlIiDtIy2HHxg11f53iqzQa6Woy0ZM2RYEKaALYlAjqI3PZ3x4pzpjKHShiyBxMGHj/D0jWZwaK+Wg8Qa4OVRzAEQ2Iwta4DvaB9JyvQU84acnSsUIC7+d3eUVxJAJnewiFvMOjQfllzt316kugazYmF/GBpDJu4 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2026 16:20:23.1708 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d3c3fa98-1032-4c66-8e9b-08df2ba1615e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH01EPF000BE949.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6356 From: Manish Honap vfio-pci-core must stay free of any CXL header dependency, so CXL Type-2 handling lives in a separate vfio-cxl module that plugs in a set of callbacks. Add the registration interface: - vfio-cxl registers a single struct vfio_cxl_ops at module_init - vfio-pci-core stores it under an rwsem. A second registration is refused with -EBUSY. The owner field will be used to pin vfio-cxl for the lifetime of each bound CXL device. Assisted-by: LLM Signed-off-by: Manish Honap --- drivers/vfio/pci/vfio_pci_core.c | 24 ++++++++++++++++++++++++ include/linux/vfio_pci_core.h | 10 ++++++++++ 2 files changed, 34 insertions(+) diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c index 6757054e9d87..2cc5dd20396c 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -2178,6 +2178,30 @@ static void vfio_pci_vga_uninit(struct vfio_pci_core_device *vdev) VGA_RSRC_LEGACY_MEM); } +static const struct vfio_cxl_ops *vfio_pci_cxl_ops; +static DECLARE_RWSEM(vfio_pci_cxl_ops_rwsem); + +int vfio_pci_core_register_cxl_ops(const struct vfio_cxl_ops *ops) +{ + guard(rwsem_write)(&vfio_pci_cxl_ops_rwsem); + + if (vfio_pci_cxl_ops) + return -EBUSY; + + vfio_pci_cxl_ops = ops; + return 0; +} +EXPORT_SYMBOL_GPL(vfio_pci_core_register_cxl_ops); + +void vfio_pci_core_unregister_cxl_ops(const struct vfio_cxl_ops *ops) +{ + guard(rwsem_write)(&vfio_pci_cxl_ops_rwsem); + + if (vfio_pci_cxl_ops == ops) + vfio_pci_cxl_ops = NULL; +} +EXPORT_SYMBOL_GPL(vfio_pci_core_unregister_cxl_ops); + int vfio_pci_core_init_dev(struct vfio_device *core_vdev) { struct vfio_pci_core_device *vdev = diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index 9a1674c152aa..9fe0d1a3a370 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -66,6 +66,16 @@ struct vfio_pci_device_ops { size_t nr_ranges); }; +struct vfio_cxl_ops { + int (*init)(struct vfio_pci_core_device *vdev); + void (*release)(struct vfio_pci_core_device *vdev); + /* Pinned per bound CXL device so vfio-cxl cannot unload under usage */ + struct module *owner; +}; + +int vfio_pci_core_register_cxl_ops(const struct vfio_cxl_ops *ops); +void vfio_pci_core_unregister_cxl_ops(const struct vfio_cxl_ops *ops); + #if IS_ENABLED(CONFIG_VFIO_PCI_DMABUF) int vfio_pci_core_fill_phys_vec(struct phys_vec *phys_vec, struct vfio_region_dma_range *dma_ranges, -- 2.53.0