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Fri, 16 Oct 2026 09:20:07 -0700 From: To: , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , Subject: [PATCH v6 08/31] vfio/pci: Add a generic excluded-range list Date: Fri, 16 Oct 2026 21:48:15 +0530 Message-ID: <20261016161839.2765592-9-mhonap@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261016161839.2765592-1-mhonap@nvidia.com> References: <20261016161839.2765592-1-mhonap@nvidia.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH01EPF000BE94C:EE_|SJ5PPF5D591B24D:EE_ X-MS-Office365-Filtering-Correlation-Id: 4f31a22d-6797-4518-9367-08df2ba16c8d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|36860700016|376014|1800799024|82310400026|7416014|22082099003|10067099003|18002099003|11063799006|261009223027099003|921020|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ZGWCV3/Fn1qO/HshpMpZ4+iM3TBeHvUZPSSBgFMhqzBs44y/xum2kWorNn+73SaQEbvqfrDutxct/bMNsuHKv1rQkhrAPUVsLcmSgzMnMWWRrbEVqFOZV7anYtC1LAz3f3rwxdA2LK1n9vm06NtiB7F9+XDzgVXhzhlXytr11f4UQxrzDWiY3F19Yque3NM2nc3TfMKaAQN8WamhVVxtobrfFTT2VfLMEY8YK6EAGhW34vyRuAGsW8wJDcWYkKVvDR+Xse+IrdvWMzNxjVB99TYdO9b9kckjaUSqan+i4MQNOwDVrqaSufbRoq7TjgG4V7MFiwoOYDz/C5xFmIDniMRyW6JzXHATdgrYG1gzsHPqAne9sF0kO4qajM2Xw3oWVMn8o0+mdVEnWsLFSBKbUAaskX6ZVWqp7enZvLnfunPSAr7EN+rqKlI8T589X2DD X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2026 16:20:41.9382 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4f31a22d-6797-4518-9367-08df2ba16c8d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH01EPF000BE94C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPF5D591B24D From: Manish Honap A provider such as vfio-cxl needs to keep sub-ranges of a BAR off the direct guest path and serve them through its own trap. vfio-pci-core already has one such window, the MSI-X table, open-coded in vfio_pci_bar_rw(). Add vfio_pci_core_add_excluded_range(). Each BAR has its own list, sorted by start, and an insert that overlaps a range on the same BAR or ends past the BAR fails with -EINVAL. Ranges are added only while the device is being opened and are freed in vfio_pci_core_disable(), so readers on an open device take no lock. The MSI-X table is virtualized in vfio_pci_bar_rw() by an open-coded x_start/x_end window that fills reads with -1 and drops writes. Register the MSI-X table as a read and write excluded range when the MSI-X capability is parsed in vfio_pci_core_enable(), and walk the BAR's ranges in order in vfio_pci_bar_rw(), so an access that spans several ranges is handled in one pass. Only the part of the table inside its BAR is registered, so a device whose MSI-X capability points outside the BAR still opens, as before. The ROM BAR keeps its trailing -1 window, outside the list. No behavioral change for an MSI-X table in a standard BAR: an access to it still reads -1 and drops writes. Assisted-by: LLM Signed-off-by: Manish Honap --- drivers/vfio/pci/vfio_pci_core.c | 97 ++++++++++++++++++++++++++++++++ drivers/vfio/pci/vfio_pci_priv.h | 8 +++ drivers/vfio/pci/vfio_pci_rdwr.c | 67 +++++++++++++++++++--- include/linux/vfio_pci_core.h | 20 +++++++ 4 files changed, 185 insertions(+), 7 deletions(-) diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c index e50b36751d9a..bee3d1b4d8d2 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -588,6 +588,8 @@ static const struct dev_pm_ops vfio_pci_core_pm_ops = { NULL) }; +static void vfio_pci_free_excluded_ranges(struct vfio_pci_core_device *vdev); + int vfio_pci_core_enable(struct vfio_pci_core_device *vdev) { struct pci_dev *pdev = vdev->pdev; @@ -644,6 +646,7 @@ int vfio_pci_core_enable(struct vfio_pci_core_device *vdev) msix_pos = pdev->msix_cap; if (msix_pos) { + u64 bar_len = 0; u16 flags; u32 table; @@ -654,6 +657,30 @@ int vfio_pci_core_enable(struct vfio_pci_core_device *vdev) vdev->msix_offset = table & PCI_MSIX_TABLE_OFFSET; vdev->msix_size = ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) * 16; vdev->has_dyn_msix = pci_msix_can_alloc_dyn(pdev); + + /* + * Virtualize the MSI-X table through the excluded-range list: + * reads fill -1 and writes are dropped so the guest never + * reaches the hardware table directly. BAR access never goes + * past the BAR, so only the part of the table inside the BAR + * needs a range; a table placed outside its BAR needs none. + */ + if (vdev->msix_bar < PCI_STD_NUM_BARS) + bar_len = pci_resource_len(pdev, vdev->msix_bar); + if (vdev->msix_offset < bar_len) { + u64 len = min_t(u64, vdev->msix_size, + bar_len - vdev->msix_offset); + + ret = vfio_pci_core_add_excluded_range(vdev, vdev->msix_bar, + vdev->msix_offset, len, + VFIO_PCI_EXCLUDE_READ | + VFIO_PCI_EXCLUDE_WRITE); + if (ret) { + vfio_pci_free_excluded_ranges(vdev); + vfio_config_free(vdev); + goto out_free_zdev; + } + } } else { vdev->msix_bar = 0xFF; vdev->has_dyn_msix = false; @@ -740,6 +767,7 @@ void vfio_pci_core_disable(struct vfio_pci_core_device *vdev) vdev->region = NULL; /* don't krealloc a freed pointer */ vfio_config_free(vdev); + vfio_pci_free_excluded_ranges(vdev); for (i = 0; i < PCI_STD_NUM_BARS; i++) { bar = i + PCI_STD_RESOURCES; @@ -1012,6 +1040,72 @@ static int msix_mmappable_cap(struct vfio_pci_core_device *vdev, return vfio_info_add_capability(caps, &header, sizeof(header)); } +/** + * vfio_pci_core_add_excluded_range() - keep a BAR sub-range off direct access + * @vdev: vfio PCI device being opened + * @bar: BAR index, below PCI_STD_NUM_BARS + * @start: offset of the range in @bar + * @size: length of the range in bytes + * @flags: VFIO_PCI_EXCLUDE_* paths the range is excluded from + * + * Call only while the device is being opened, from vfio_pci_core_enable() or + * a provider's open hook; vfio_pci_core_disable() frees the ranges. Ranges on + * one BAR must not overlap and must lie inside the BAR. + * + * Return: 0 on success, -EINVAL for an invalid or overlapping range or one + * that ends past the BAR, or -ENOMEM. + */ +int vfio_pci_core_add_excluded_range(struct vfio_pci_core_device *vdev, int bar, + u64 start, u64 size, u32 flags) +{ + const u32 valid = VFIO_PCI_EXCLUDE_MMAP | VFIO_PCI_EXCLUDE_READ | + VFIO_PCI_EXCLUDE_WRITE; + struct vfio_pci_excluded_range *range, *pos; + struct list_head *head; + + if (bar < 0 || bar >= PCI_STD_NUM_BARS || !size || + start + size < start || !flags || (flags & ~valid)) + return -EINVAL; + if (start + size > pci_resource_len(vdev->pdev, bar)) + return -EINVAL; + + /* Keep the list sorted by start; find the first range after @start. */ + head = &vdev->excluded_ranges[bar]; + list_for_each_entry(pos, head, entry) { + if (start < pos->start + pos->size && start + size > pos->start) + return -EINVAL; + if (pos->start > start) + break; + } + + range = kmalloc_obj(*range); + if (!range) + return -ENOMEM; + + *range = (struct vfio_pci_excluded_range) { + .start = start, + .size = size, + .flags = flags, + }; + list_add_tail(&range->entry, &pos->entry); + + return 0; +} +EXPORT_SYMBOL_GPL(vfio_pci_core_add_excluded_range); + +static void vfio_pci_free_excluded_ranges(struct vfio_pci_core_device *vdev) +{ + struct vfio_pci_excluded_range *range, *tmp; + + for (int bar = 0; bar < PCI_STD_NUM_BARS; bar++) { + list_for_each_entry_safe(range, tmp, &vdev->excluded_ranges[bar], + entry) { + list_del(&range->entry); + kfree(range); + } + } +} + int vfio_pci_core_register_dev_region(struct vfio_pci_core_device *vdev, unsigned int type, unsigned int subtype, const struct vfio_pci_regops *ops, @@ -2317,6 +2411,8 @@ int vfio_pci_core_init_dev(struct vfio_device *core_vdev) INIT_LIST_HEAD(&vdev->dmabufs); init_rwsem(&vdev->memory_lock); xa_init(&vdev->ctx); + for (int bar = 0; bar < PCI_STD_NUM_BARS; bar++) + INIT_LIST_HEAD(&vdev->excluded_ranges[bar]); ret = vfio_pci_core_cxl_init(vdev); if (ret) @@ -2332,6 +2428,7 @@ void vfio_pci_core_release_dev(struct vfio_device *core_vdev) container_of(core_vdev, struct vfio_pci_core_device, vdev); vfio_pci_core_cxl_release(vdev); + vfio_pci_free_excluded_ranges(vdev); mutex_destroy(&vdev->igate); mutex_destroy(&vdev->ioeventfds_lock); diff --git a/drivers/vfio/pci/vfio_pci_priv.h b/drivers/vfio/pci/vfio_pci_priv.h index 4e7162234a2e..53544e0cbedf 100644 --- a/drivers/vfio/pci/vfio_pci_priv.h +++ b/drivers/vfio/pci/vfio_pci_priv.h @@ -44,6 +44,14 @@ ssize_t vfio_pci_config_rw_single(struct vfio_pci_core_device *vdev, ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device *vdev, char __user *buf, size_t count, loff_t *ppos, bool iswrite); +/* A BAR sub-range kept off direct access; see vfio_pci_core_add_excluded_range() */ +struct vfio_pci_excluded_range { + struct list_head entry; + u64 start; + u64 size; + u32 flags; +}; + #ifdef CONFIG_VFIO_PCI_VGA ssize_t vfio_pci_vga_rw(struct vfio_pci_core_device *vdev, char __user *buf, size_t count, loff_t *ppos, bool iswrite); diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c b/drivers/vfio/pci/vfio_pci_rdwr.c index 7f14dd46de17..93823c6391f6 100644 --- a/drivers/vfio/pci/vfio_pci_rdwr.c +++ b/drivers/vfio/pci/vfio_pci_rdwr.c @@ -198,6 +198,57 @@ ssize_t vfio_pci_core_do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem, } EXPORT_SYMBOL_GPL(vfio_pci_core_do_io_rw); +/* + * Access @count bytes of @bar at @pos, walking the BAR's excluded ranges in + * order: a range excluded for this direction reads as -1 and drops writes, + * and the bytes around it reach the device. The MSI-X table is one such + * range, and a BAR can hold several, for example the MSI-X table and a CXL + * HDM decoder block. + */ +static ssize_t vfio_pci_bar_do_io_rw(struct vfio_pci_core_device *vdev, + int bar, bool test_mem, void __iomem *io, + char __user *buf, loff_t pos, + size_t count, bool iswrite, + enum vfio_pci_io_width max_width) +{ + u32 want = iswrite ? VFIO_PCI_EXCLUDE_WRITE : VFIO_PCI_EXCLUDE_READ; + struct vfio_pci_excluded_range *range; + ssize_t done = 0; + ssize_t ret; + + list_for_each_entry(range, &vdev->excluded_ranges[bar], entry) { + u64 end = range->start + range->size; + size_t chunk; + + if (!(range->flags & want) || end <= pos) + continue; + if (range->start >= pos + count) + break; + + /* Up to the end of this range; do_io_rw() fills it. */ + chunk = min_t(u64, count, end - pos); + ret = vfio_pci_core_do_io_rw(vdev, test_mem, io, buf, pos, chunk, + range->start, end, iswrite, + max_width); + if (ret < 0) + return done ?: ret; + + done += ret; + pos += ret; + buf += ret; + count -= ret; + if (!count) + return done; + } + + ret = vfio_pci_core_do_io_rw(vdev, test_mem, io, buf, pos, count, 0, 0, + iswrite, max_width); + if (ret < 0) + return done ?: ret; + + return done + ret; +} + ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device *vdev, char __user *buf, size_t count, loff_t *ppos, bool iswrite) { @@ -256,13 +307,15 @@ ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device *vdev, char __user *buf, } } - if (bar == vdev->msix_bar) { - x_start = vdev->msix_offset; - x_end = vdev->msix_offset + vdev->msix_size; - } - - done = vfio_pci_core_do_io_rw(vdev, res->flags & IORESOURCE_MEM, io, buf, pos, - count, x_start, x_end, iswrite, max_width); + if (bar == PCI_ROM_RESOURCE) + done = vfio_pci_core_do_io_rw(vdev, res->flags & IORESOURCE_MEM, + io, buf, pos, count, x_start, + x_end, iswrite, max_width); + else + done = vfio_pci_bar_do_io_rw(vdev, bar, + res->flags & IORESOURCE_MEM, io, + buf, pos, count, iswrite, + max_width); if (done >= 0) *ppos += done; diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index 7f3a2bcb5830..70acb03d466e 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -162,6 +162,13 @@ struct vfio_pci_core_device { struct notifier_block nb; struct rw_semaphore memory_lock; struct list_head dmabufs; + /* + * Excluded BAR sub-ranges, one list per BAR, sorted by start and not + * overlapping. The lists are filled only while the device is being + * opened and emptied in vfio_pci_core_disable(); every reader runs on + * an open device in between, so readers take no lock. + */ + struct list_head excluded_ranges[PCI_STD_NUM_BARS]; }; enum vfio_pci_io_width { @@ -172,6 +179,19 @@ enum vfio_pci_io_width { }; /* Will be exported for vfio pci drivers usage */ +/* + * A provider can keep a BAR sub-range off the direct guest path, reached only + * through its own trap. The flags select which paths are excluded: mmap, and + * region read and write (an excluded read fills -1, an excluded write is + * dropped). + */ +#define VFIO_PCI_EXCLUDE_MMAP BIT(0) +#define VFIO_PCI_EXCLUDE_READ BIT(1) +#define VFIO_PCI_EXCLUDE_WRITE BIT(2) + +int vfio_pci_core_add_excluded_range(struct vfio_pci_core_device *vdev, int bar, + u64 start, u64 size, u32 flags); + int vfio_pci_core_register_dev_region(struct vfio_pci_core_device *vdev, unsigned int type, unsigned int subtype, const struct vfio_pci_regops *ops, -- 2.53.0