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Wed, 21 Oct 2026 21:17:28 -0700 (PDT) Received: from localhost.localdomain ([2600:1700:4577:1050:cde2:63f1:eb1b:b344]) by smtp.gmail.com with ESMTPSA id 00721157ae682-8b142cf9708sm10230967b3.4.2026.10.21.21.17.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 21 Oct 2026 21:17:27 -0700 (PDT) From: Ravi Jonnalagadda To: sj@kernel.org Cc: corbet@lwn.net, damon@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, rdunlap@infradead.org, skhan@linuxfoundation.org, Ravi Jonnalagadda Subject: Re: [RFC PATCH v0] Docs/mm/damon/design: document data attributes report infra design (beyond page table accessed-bit milestone 2) Date: Wed, 21 Oct 2026 21:17:24 -0700 Message-ID: <20261022041724.2712-1-ravis.opensrc@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20261017195747.89961-1-sj@kernel.org> References: <20261017195747.89961-1-sj@kernel.org> X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi SJ, Thank you for sharing the design early. Short version: the design makes sense to me, with one main suggestion. The first report type should use the data address the PMU captures at sample time, rather than decode the instruction later in kdamond. The measurements behind it are in my reply to your answer to sashiko. On Sat, 17 Oct 2026 12:57:45 -0700 SJ Park wrote: > Does the idea for perf CPU cycle sampling based access monitoring makes > sense? On AMD, yes, with precise_ip (cpu-cycles:p routes to IBS Op): its memory-op samples carry a data address and load/store type. On Intel, even precise cycles samples (cycles:pp) carry no data address; PEBS memory events do. Decode from saved registers worked for one of two test loops on Intel and for neither on AMD (details in the other reply), hence the suggestion above. > Does the design provides clear idea about how it can be extended for the > future extensions that already scoped for milestone 3 (AMD IBS, Intel > PEBS, Arm SPE)? Yes, if the report has an address field with a validity bit and carries the producing report-type (attr) id. Then IBS, PEBS, Arm SPE (through an adapter, since SPE uses the perf AUX buffer) and device-side monitors all produce the same report, into the same queues and probes. > For the foreseeable extensions (AMD IBS, Intel PEBS, Arm SPE), would the > required change minimum and maintainable? Yes, if staged. The sample-filter matcher and its sysfs already exist per context; attaching them per probe is the main change. For example: M2.1 in-kernel only: damon_report_attrs(), the queue, region lookup, the perf producer; kunit, no new sysfs M2.2 your per-CPU write-only example, set up from user space: attr_reports files, per-filter report_queue, write/cpumask/threads probe filters M2.3 counters, a silence check (tracepoint/debugfs first), tuning M3 more producers: Arm SPE, device monitors Implementation notes: 1. One sampler per CPU per attr, owned by attr_reports (as in your damon/next usage doc) and shared by all contexts. IBS has one unit per CPU, so perf time-slices multiple events: on EPYC 9555P one ibs_op event got 67,140 samples; two on the same CPU got 33,547 + 33,535. On Intel the event also needs wakeup_events = 1, or an in-kernel handler sees only the last record of each large-PEBS batch. 2. A lockless queue, as your NOTE in damon_report_access() anticipates. Today's buffer is documented "May sleep" and uses mutex_trylock(), which interrupt context cannot use; its inclusive jiffy staleness check can also count one report in up to three intervals (HZ=250, 5 ms interval). A simple design: a per-CPU circular array with a write counter and a per-slot seqcount_t (using raw_write_seqcount_begin/end() for NMI safety), overwriting the oldest slot. Readers never consume; each context keeps its last-seen write counter per CPU. A nested writer (e.g. an NMI over a task-context write) drops its report and counts it. 3. Report fields: paddr, vaddr, size, time, cpu, tid, tgid, the producer's attr id, and flags (is_write, plus a validity bit per address, since 0 is a valid paddr). Store global ids; translate namespaces at the filter. 4. Binary search over a sorted region snapshot (your todo in kdamond_apply_access_report()) beats a linear walk from about 2 reports per interval for 1,000 regions (a model, to be measured). 5. Samplers can stop silently: in a report on the v4 thread [1], IBS Op samples stopped after about 10 minutes on a Ryzen 5 5600H, but not with the NMI watchdog enabled. So count dropped reports and check for silence against an independent reference. For tuning, step sample_period rather than use frequency mode, and do not raise perf_event_max_sample_rate: on an early DAMON PEBS prototype (Xeon 6960P), perf cut it from 100000 to 10000 in about 20 seconds. Three decisions would unblock M2.1: - The first report type: the PMU-captured address (suggested), or decode from saved registers in kdamond (your current plan). - Whether the report carries the producer's attr id (suggested: yes). - The queue: the per-CPU seqcount design in note 2 (suggested), or ftrace's ring buffer with one iterator per reader. One question on the ABI: the usage document in your damon/next tree adds a report_queue file under each probe filter. Is it meant as "this filter tests reports in queue N"? Happy to write, review or test any piece: the queue with kunit, the AMD/Intel perf producer, a decode-accuracy study on real workloads, or runs on Xeon 6960P and EPYC 9555P. Several exist in RFC v4 [2]. Thanks, Ravi [1] https://lore.kernel.org/r/20261017211613.16456-2-aethernet65535@gmail.com [2] https://lore.kernel.org/r/20261005-damon-perf-rfc-v3-send-2026-10-03-v4-0-b03452e137f3@gmail.com