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Fri, 4 Jul 2025 18:14:30 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v8 23/29] iommu/arm-smmu-v3-iommufd: Add vsmmu_size/type and vsmmu_init impl ops Date: Fri, 4 Jul 2025 18:13:39 -0700 Message-ID: <215ea3fd9beb2e2fb0454133024d171e376e7e62.1751677708.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4A:EE_|PH8PR12MB7326:EE_ X-MS-Office365-Filtering-Correlation-Id: 7a0bb4c1-b082-40da-6d71-08ddbb61527b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?FB5MtJjC5oBu2J3UjUsc99sQXkM+Y3wG/40HwjROWvGA9rQPzNIGse93CuWT?= =?us-ascii?Q?7zsKuBHzgdOfHCj4lOqvqveyq8j41dj0BTMtELha0zZJCTdRIl0at2v0T537?= =?us-ascii?Q?o9rE2ZliAM5LECuJr/u/guqIDAL7t3V3gDBqh+VH3f76W9mhVCvWivmEkjiQ?= =?us-ascii?Q?G1QnGcCmDt6sJ3cI3wO4H8iVzfOFmToIhB0asqT4wYSg1JBXFHuu6Prhhzw+?= =?us-ascii?Q?tH8hoSheIOELlVxVV0zgWOz19T1uYkG7hw7QzS2c6cmL5vRUCjIaHXlRzsfq?= =?us-ascii?Q?yBJuU7Q2W3zbC7w/vuilcss6k65S5KLt/UuwB/PCLP4GWs3fpuNrHtn46Fbu?= =?us-ascii?Q?iCpIqOhPuD5lFBKGxr65W+qhIqUVdOkVQ9f6H4bjbdd7Lk2CMp5AkRbjmgqN?= =?us-ascii?Q?Q1c+lBtSGUw+WbeEjzsYs9MbsT9I9rGtK4md9MF+DHkV4jNJu7MSQ9W3brla?= =?us-ascii?Q?pItimctfQGNCDafmvwoGGrlMbxjIKuh5wbnseOsbzTwmf5wCnJCmR1xhIq90?= =?us-ascii?Q?eSDuK3jKE0YxfmFE0136uh0m6JbJ4uAjCYCHDfS2YXD9lEehq6Fe//Fu+3NL?= =?us-ascii?Q?I2uuJErisPsmttijvTvdGIj1Iys33irMWtemOGHBzpzG5JMk43dMloabCHsb?= =?us-ascii?Q?OZ1H1pipPBKC92ChAYEJ46oOCzbPuRP4Armv4lNQYkIFA3AjIV5o17H6UyZj?= =?us-ascii?Q?AM8rEggvYXaclGePspy5KO+E5odzxl1SaocMwzW/dGjrHAMIctPkAvsg8JCg?= =?us-ascii?Q?1juH23q0Zs5aRyE6CEay4wDg/MJFWXALJAqJWwH25AFjn9l8fM0clzanbLE8?= =?us-ascii?Q?s8qWrbF8lC5r1n83IgPaZOUkQPDK8x9K2V8O6KgaKmcct3B/RS1KqoLap6T7?= =?us-ascii?Q?sDTparwPJ9bR4m6bf3UgZV4VW9KxT6B9fATO8KKnX6FFRHYP0vW1/heKAUPR?= =?us-ascii?Q?5tYqyB/2a4pWA1KOfH8tTUjYDwC/soYIGQRYlTWVKd+KChgeZsJ49HAK6val?= =?us-ascii?Q?8PdQ1hl27ZXPTycTdjgUPfPsRKXY0y0HECVZdVctNkFJKnwx3rtZ+3JMxd3W?= =?us-ascii?Q?GcDl3KEMtaJ0rXozm+5z5UT47V2TEu2Z/M5yJ+BG2TsTzEbYGkkKvTiB8TeA?= =?us-ascii?Q?v1FOrKj01zQvKeltyAPXmZLsFyXCwZVZN0jIh7RTJiotAqmPKPfsQ4G5zn0r?= =?us-ascii?Q?NSyK7Rts1f5wKCWliHMPJjfMNXUMmyW3zAjje/9egse82cvkIhxHkzl9ETXi?= =?us-ascii?Q?ZeY3kOp8ohvdaBMTUS2yqIe5wZKywqIJm4Do69rgOwRErFjqA+zWlvRirEKg?= =?us-ascii?Q?XqEyRLYSKmK/QC7UGcyCaEhhTIpu20NiOgg07JWY2seqNzcEYgtLnebTO2sG?= =?us-ascii?Q?oX8IJkctXkIwedBdmm2Bs2AWardpZbpVpCaiOBx6uHU3jo7+w0Qheq+kccZU?= =?us-ascii?Q?VIWqvueTy5qbYtsBWa7AM7cor4vm3bhW5uMAC5a+uqt4cHUwUAu+RwcjhWkk?= =?us-ascii?Q?OyQLPUdqIJtXFPpFJEeEBpj2Y+cbFg2xF1kn?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jul 2025 01:14:42.4665 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a0bb4c1-b082-40da-6d71-08ddbb61527b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7326 An impl driver might want to allocate its own type of vIOMMU object or the standard IOMMU_VIOMMU_TYPE_ARM_SMMUV3 by setting up its own SW/HW bits, as the tegra241-cmdqv driver will add IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV. Add vsmmu_size/type and vsmmu_init to struct arm_smmu_impl_ops. Prioritize them in arm_smmu_get_viommu_size() and arm_vsmmu_init(). Reviewed-by: Pranjal Shrivastava Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 5 +++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 8 ++++++++ 2 files changed, 13 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 7eed5c8c72dd..07589350b2a1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -16,6 +16,7 @@ #include struct arm_smmu_device; +struct arm_vsmmu; /* MMIO registers */ #define ARM_SMMU_IDR0 0x0 @@ -720,6 +721,10 @@ struct arm_smmu_impl_ops { int (*init_structures)(struct arm_smmu_device *smmu); struct arm_smmu_cmdq *(*get_secondary_cmdq)( struct arm_smmu_device *smmu, struct arm_smmu_cmdq_ent *ent); + const size_t vsmmu_size; + const enum iommu_viommu_type vsmmu_type; + int (*vsmmu_init)(struct arm_vsmmu *vsmmu, + const struct iommu_user_data *user_data); }; /* An SMMUv3 instance */ diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index eb9fe1f6311a..2ab1c6cf4aac 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -416,6 +416,10 @@ size_t arm_smmu_get_viommu_size(struct device *dev, !(smmu->features & ARM_SMMU_FEAT_S2FWB)) return 0; + if (smmu->impl_ops && smmu->impl_ops->vsmmu_size && + viommu_type == smmu->impl_ops->vsmmu_type) + return smmu->impl_ops->vsmmu_size; + if (viommu_type != IOMMU_VIOMMU_TYPE_ARM_SMMUV3) return 0; @@ -439,6 +443,10 @@ int arm_vsmmu_init(struct iommufd_viommu *viommu, /* FIXME Move VMID allocation from the S2 domain allocation to here */ vsmmu->vmid = s2_parent->s2_cfg.vmid; + if (smmu->impl_ops && smmu->impl_ops->vsmmu_init && + viommu->type == smmu->impl_ops->vsmmu_type) + return smmu->impl_ops->vsmmu_init(vsmmu, user_data); + viommu->ops = &arm_vsmmu_ops; return 0; } -- 2.43.0