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Tue, 13 Oct 2026 21:29:45 +0000 Message-ID: <22ecec13-a703-414e-9f5e-75c89173e845@intel.com> Date: Tue, 13 Oct 2026 14:29:41 -0700 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 2/5] riscv_cbqri: resctrl: Add cache allocation via capacity block mask To: "Luck, Tony" CC: Drew Fustini , Adrien Ricciardi , Alexandre Ghiti , Atish Kumar Patra , Atish Patra , Babu Moger , Ben Horgan , Borislav Petkov , Chen Pei , Conor Dooley , Conor Dooley , Dave Hansen , Dave Martin , Fenghua Yu , Gong Shuai , Gong Shuai , "guo.wenjia23@zte.com.cn" , James Morse , =?UTF-8?Q?Kornel_Dul=C4=99ba?= , Krzysztof Kozlowski , "liu.qingtao2@zte.com.cn" , Liu Zhiwei , Palmer Dabbelt , "Paul Walmsley" , Peter Newman , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Rob Herring , Samuel Holland , "Sebastian Andrzej Siewior" , Vasudevan Srinivasan , Ved Shanbhogue , Weiwei Li , yunhui cui , Zhanpeng Zhang , "linux-kernel@vger.kernel.org" , "linux-riscv@lists.infradead.org" , "x86@kernel.org" , "devicetree@vger.kernel.org" , "linux-rt-devel@lists.linux.dev" , "linux-doc@vger.kernel.org" References: <20260901-dfustini-atl-sc-cbqri-dt-v7-0-ca2935d85622@kernel.org> <20260901-dfustini-atl-sc-cbqri-dt-v7-2-ca2935d85622@kernel.org> <8230dae2-2cb0-4b46-8cec-dc4e281d4e4a@intel.com> From: Reinette Chatre Content-Language: en-US In-Reply-To: Content-Type: text/plain; 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The implementation of that has a couple of choices: > > 1) Ignore 25% of the caches on the E-cores. > Unlikely to please anyone. Just like the percentage based memory bandwidth control is not able to please everybody but it is something that can be exposed to not break userspace while it can be emulated with the underlying hardware controls. Users needing finer grained capability will have the option to switch to the native controls. > 2) Silently allow access to the "f000" ways of the E-core caches. > Doesn't waste the hardware, but if the user tries to divide > available cache exclusively between groups, the "free" extra > cache would result in surprise sharing. (2) requires the system to support sparse bitmasks. > > The drive for L2 controls on hybrid systems comes from embedded systems > where expectations would be for the controls to operate precisely as > written without any fuzziness. > > I'm not seeing a market for the legacy behavior, so implementing it > would just add complexity to resctrl without any benefit to users. > > Perhaps keep the "L2" resource name. Use "L2" for a control name for > symmetric systems. Use "L2A" as the control name for asymmetric systems. > Legacy software won't be confused because there won't be an "L2:" > line in the schemata file. This cannot simultaneously be a market that does not require legacy behavior and require legacy software to not be confused. Unfortunately I believe legacy software (which is the latest software today) will get confused. I understand that there are many different utilities used to interact with resctrl so behavior can vary. Based on my understanding of the pqos/intel-cmt-cat utility the system's capabilities are determined by parsing /sys/fs/resctrl/info. Based on this parsing the utility expects particular entries to exist in schemata file and interacts with schemata file with this expectation without checking whether a matching entry is actually in schemata file or not. The utility will thus inform user space that L2 CAT is fully available but when user space attempts any read/write the behavior will be unexpected. > > Don't bother with a control_mode to switch between legacy and native. > Just auto-select the "L2A" control on asymmetric systems. > > But since this thread started from a RISC-V thread, it would be good to > hear what is needed for RISC-V. ack. Reinette