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([2620:15c:211:201:8a44:a3e:c994:3f4b]) by smtp.gmail.com with ESMTPSA id k16-20020aa79d10000000b0050dc7628162sm17863699pfp.60.2022.06.09.13.34.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Jun 2022 13:34:33 -0700 (PDT) Message-ID: <23bf4427-41c3-bf1d-903a-75928bb47627@acm.org> Date: Thu, 9 Jun 2022 13:34:31 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.0 Subject: Re: [PATCH v3 3/4] scsi: core: Cap shost max_sectors according to DMA optimum mapping limits Content-Language: en-US To: John Garry , damien.lemoal@opensource.wdc.com, joro@8bytes.org, will@kernel.org, jejb@linux.ibm.com, martin.petersen@oracle.com, hch@lst.de, m.szyprowski@samsung.com, robin.murphy@arm.com Cc: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-ide@vger.kernel.org, iommu@lists.linux-foundation.org, linux-scsi@vger.kernel.org, liyihang6@hisilicon.com, chenxiang66@hisilicon.com, thunder.leizhen@huawei.com References: <1654507822-168026-1-git-send-email-john.garry@huawei.com> <1654507822-168026-4-git-send-email-john.garry@huawei.com> <31417477-953d-283e-808e-cf8701e820a8@huawei.com> <5b214e95-dd95-551a-496e-a2139a74e8eb@huawei.com> <9b1d155e-28cc-08dc-5a5a-8580132575e7@huawei.com> From: Bart Van Assche In-Reply-To: <9b1d155e-28cc-08dc-5a5a-8580132575e7@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org On 6/9/22 10:54, John Garry wrote: > ok, but do you have a system where the UFS host controller is behind an > IOMMU? I had the impression that UFS controllers would be mostly found > in embedded systems and IOMMUs are not as common on there. Modern phones have an IOMMU. Below one can find an example from a Pixel 6 phone. The UFS storage controller is not controller by the IOMMU as far as I can see but I wouldn't be surprised if the security team would ask us one day to enable the IOMMU for the UFS controller. # (cd /sys/class/iommu && ls */devices) 1a090000.sysmmu/devices: 19000000.aoc 1a510000.sysmmu/devices: 1a440000.lwis_csi 1a540000.sysmmu/devices: 1aa40000.lwis_pdp 1a880000.sysmmu/devices: 1a840000.lwis_g3aa 1ad00000.sysmmu/devices: 1ac40000.lwis_ipp 1ac80000.lwis_gtnr_align 1b080000.sysmmu/devices: 1b450000.lwis_itp 1b780000.sysmmu/devices: 1b7b0000.sysmmu/devices: 1b760000.lwis_mcsc 1b7e0000.sysmmu/devices: 1baa0000.sysmmu/devices: 1a4e0000.lwis_votf 1ba40000.lwis_gdc 1bad0000.sysmmu/devices: 1ba60000.lwis_gdc 1bb00000.sysmmu/devices: 1ba80000.lwis_scsc 1bc70000.sysmmu/devices: 1bc40000.lwis_gtnr_merge 1bca0000.sysmmu/devices: 1bcd0000.sysmmu/devices: 1bd00000.sysmmu/devices: 1bd30000.sysmmu/devices: 1c100000.sysmmu/devices: 1c300000.drmdecon 1c302000.drmdecon 1c110000.sysmmu/devices: 1c120000.sysmmu/devices: 1c660000.sysmmu/devices: 1c640000.g2d 1c690000.sysmmu/devices: 1c710000.sysmmu/devices: 1c700000.smfc 1c870000.sysmmu/devices: 1c8d0000.MFC-0 mfc 1c8a0000.sysmmu/devices: 1ca40000.sysmmu/devices: 1cb00000.bigocean 1cc40000.sysmmu/devices: 1ce00000.abrolhos Bart.