From: "Clément Léger" <cleger@rivosinc.com>
To: Inochi Amaoto <inochiama@gmail.com>,
Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Evan Green <evan@rivosinc.com>,
Charlie Jenkins <charlie@rivosinc.com>,
Andrew Jones <ajones@ventanamicro.com>,
Andy Chiu <andybnac@gmail.com>, Xiao Wang <xiao.w.wang@intel.com>,
Samuel Holland <samuel.holland@sifive.com>
Cc: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Yixun Lan <dlan@gentoo.org>, Longbin Li <looong.bin@gmail.com>
Subject: Re: [PATCH v2 2/3] riscv: add ISA extension parsing for bfloat16 ISA extension
Date: Mon, 4 Nov 2024 10:15:56 +0100 [thread overview]
Message-ID: <2e775421-0c3e-48ef-8a8c-6734f7fcf298@rivosinc.com> (raw)
In-Reply-To: <20241103074959.1135240-3-inochiama@gmail.com>
On 03/11/2024 08:49, Inochi Amaoto wrote:
> Add parsing for Zfbmin, Zvfbfmin, Zvfbfwma ISA extension which
> were ratified in 4dc23d62 ("Added Chapter title to BF16") of
> the riscv-isa-manual.
>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> ---
> arch/riscv/include/asm/hwcap.h | 3 +++
> arch/riscv/kernel/cpufeature.c | 3 +++
> 2 files changed, 6 insertions(+)
>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 46d9de54179e..97657fb63af6 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -93,6 +93,9 @@
> #define RISCV_ISA_EXT_ZCMOP 84
> #define RISCV_ISA_EXT_ZAWRS 85
> #define RISCV_ISA_EXT_SVVPTC 86
> +#define RISCV_ISA_EXT_ZFBFMIN 87
> +#define RISCV_ISA_EXT_ZVFBFMIN 88
> +#define RISCV_ISA_EXT_ZVFBFWMA 89
>
> #define RISCV_ISA_EXT_XLINUXENVCFG 127
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 3a8eeaa9310c..1b286f5bc591 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -325,6 +325,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
> __RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS),
> __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
> + __RISCV_ISA_EXT_DATA(zfbfmin, RISCV_ISA_EXT_ZFBFMIN),
> __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
> __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
> __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA),
> @@ -357,6 +358,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
> __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
> __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
> + __RISCV_ISA_EXT_DATA(zvfbfmin, RISCV_ISA_EXT_ZVFBFMIN),
> + __RISCV_ISA_EXT_DATA(zvfbfwma, RISCV_ISA_EXT_ZVFBFWMA),
@Conor,
Should we wait for your V/F validation support to be merged before this
one ?
Thanks,
Clément
> __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
> __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
> __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
next prev parent reply other threads:[~2024-11-04 9:16 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-03 7:49 [PATCH v2 0/3] riscv: Add bfloat16 instruction support Inochi Amaoto
2024-11-03 7:49 ` [PATCH v2 1/3] dt-bindings: riscv: add bfloat16 ISA extension description Inochi Amaoto
2024-11-04 12:08 ` Conor Dooley
2024-11-03 7:49 ` [PATCH v2 2/3] riscv: add ISA extension parsing for bfloat16 ISA extension Inochi Amaoto
2024-11-04 9:15 ` Clément Léger [this message]
2024-11-04 12:07 ` Conor Dooley
2024-11-03 7:49 ` [PATCH v2 3/3] riscv: hwprobe: export " Inochi Amaoto
2024-11-04 12:11 ` Clément Léger
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=2e775421-0c3e-48ef-8a8c-6734f7fcf298@rivosinc.com \
--to=cleger@rivosinc.com \
--cc=ajones@ventanamicro.com \
--cc=andybnac@gmail.com \
--cc=aou@eecs.berkeley.edu \
--cc=charlie@rivosinc.com \
--cc=conor@kernel.org \
--cc=corbet@lwn.net \
--cc=devicetree@vger.kernel.org \
--cc=dlan@gentoo.org \
--cc=evan@rivosinc.com \
--cc=inochiama@gmail.com \
--cc=krzk+dt@kernel.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=looong.bin@gmail.com \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh@kernel.org \
--cc=samuel.holland@sifive.com \
--cc=xiao.w.wang@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox