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([2600:8803:e7e4:1d00:f7b4:dfbd:5110:c59d]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-61e357137d6sm160026eaf.4.2025.08.30.09.49.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 30 Aug 2025 09:49:23 -0700 (PDT) Message-ID: <34c23490-470d-45b1-a8a6-e9e1ee82f5c8@baylibre.com> Date: Sat, 30 Aug 2025 11:49:21 -0500 Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 03/15] Documentation: iio: ad4030: Add double PWM SPI offload doc To: Marcelo Schmitt , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, linux-spi@vger.kernel.org Cc: jic23@kernel.org, Michael.Hennerich@analog.com, nuno.sa@analog.com, eblanc@baylibre.com, andy@kernel.org, corbet@lwn.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, broonie@kernel.org, Jonathan.Cameron@huawei.com, andriy.shevchenko@linux.intel.com, ahaslam@baylibre.com, marcelo.schmitt1@gmail.com References: <4425996699ceca9fa909bdad86b41abe8b25aad4.1756511030.git.marcelo.schmitt@analog.com> Content-Language: en-US From: David Lechner In-Reply-To: <4425996699ceca9fa909bdad86b41abe8b25aad4.1756511030.git.marcelo.schmitt@analog.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 8/29/25 7:41 PM, Marcelo Schmitt wrote: > Document double PWM setup SPI offload wiring schema. > > Signed-off-by: Marcelo Schmitt > --- > Documentation/iio/ad4030.rst | 29 +++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/Documentation/iio/ad4030.rst b/Documentation/iio/ad4030.rst > index b57424b650a8..dc3ac253ef66 100644 > --- a/Documentation/iio/ad4030.rst > +++ b/Documentation/iio/ad4030.rst > @@ -92,6 +92,35 @@ Interleaved mode > In this mode, both channels conversion results are bit interleaved one SDO line. > As such the wiring is the same as `One lane mode`_. > > +SPI offload wiring > +^^^^^^^^^^^^^^^^^^ > + > +.. code-block:: > + > + +-------------+ +-------------+ > + | CNV |<-----+--| GPIO | > + | | +--| PWM1 | Would be more logical to swap the PWM numbers since CNV is triggered first. > + | | | | > + | | +--| PWM0 | > + | | | +-------------+ > + | | +->| TRIGGER | > + | CS |<--------| CS | > + | | | | > + | ADC | | SPI | > + | | | | > + | SDI |<--------| SDO | > + | SDO |-------->| SDI | > + | SCLK |<--------| SCLK | > + +-------------+ +-------------+ > + > +In this mode, both the ``cnv-gpios`` and a ``pwms`` properties are required. > +The ``pwms`` property specifies the PWM that is connected to the ADC CNV pin. > +The SPI offload will have a ``trigger-sources`` property to indicate the SPI > +offload (PWM) trigger source. The IIO device driver synchronizes the PWMs to do suggest to add something like: with an offset between the rising edge of PWM0 and PWM1 to delay the SPI transfer until some time after the conversion. This requires a specialized PWM controller that can provide such an offset. > +ADC transfer zone 2 data capture. What is "zone 2"? > + > +.. seealso:: `SPI offload support`_ There is no section that this links to. Add the section or delete this. > + > SPI Clock mode > -------------- >