From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on archive.lwn.net X-Spam-Level: X-Spam-Status: No, score=-6.0 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by archive.lwn.net (Postfix) with ESMTP id B251D7D2EF for ; Fri, 7 Jun 2019 16:22:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729676AbfFGQWx (ORCPT ); Fri, 7 Jun 2019 12:22:53 -0400 Received: from mga12.intel.com ([192.55.52.136]:57740 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728486AbfFGQWx (ORCPT ); Fri, 7 Jun 2019 12:22:53 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Jun 2019 09:22:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,563,1557212400"; d="scan'208";a="182719233" Received: from yyu32-desk1.sc.intel.com ([143.183.136.147]) by fmsmga002.fm.intel.com with ESMTP; 07 Jun 2019 09:22:52 -0700 Message-ID: <388e702bfa4ed38f460327ae09ebc9b18b582bb5.camel@intel.com> Subject: Re: [PATCH v7 05/27] x86/fpu/xstate: Add XSAVES system states for shadow stack From: Yu-cheng Yu To: Peter Zijlstra Cc: x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Randy Dunlap , "Ravi V. Shankar" , Vedvyas Shanbhogue , Dave Martin Date: Fri, 07 Jun 2019 09:14:50 -0700 In-Reply-To: <20190607070725.GN3419@hirez.programming.kicks-ass.net> References: <20190606200646.3951-1-yu-cheng.yu@intel.com> <20190606200646.3951-6-yu-cheng.yu@intel.com> <20190607070725.GN3419@hirez.programming.kicks-ass.net> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.1-2 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-doc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org On Fri, 2019-06-07 at 09:07 +0200, Peter Zijlstra wrote: > On Thu, Jun 06, 2019 at 01:06:24PM -0700, Yu-cheng Yu wrote: > > Intel Control-flow Enforcement Technology (CET) introduces the > > following MSRs. > > > > MSR_IA32_U_CET (user-mode CET settings), > > MSR_IA32_PL3_SSP (user-mode shadow stack), > > MSR_IA32_PL0_SSP (kernel-mode shadow stack), > > MSR_IA32_PL1_SSP (Privilege Level 1 shadow stack), > > MSR_IA32_PL2_SSP (Privilege Level 2 shadow stack). > > > > Introduce them into XSAVES system states. > > > > Signed-off-by: Yu-cheng Yu > > --- > > arch/x86/include/asm/fpu/types.h | 22 +++++++++++++++++++++ > > arch/x86/include/asm/fpu/xstate.h | 4 +++- > > arch/x86/include/uapi/asm/processor-flags.h | 2 ++ > > arch/x86/kernel/fpu/xstate.c | 10 ++++++++++ > > 4 files changed, 37 insertions(+), 1 deletion(-) > > And yet, no changes to msr-index.h !? You are right. I will move msr-index.h changes to here. Yu-cheng