Re: [PATCH v8 06/14] riscv: misaligned: request misaligned exception from SBI

[Vivian Wang <wangruikang@iscas.ac.cn>]

Hi Clément and riscv maintainers:

On 5/23/25 18:19, Clément Léger wrote:
> Now that the kernel can handle misaligned accesses in S-mode, request
> misaligned access exception delegation from SBI. This uses the FWFT SBI
> extension defined in SBI version 3.0.
>
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> ---
>  arch/riscv/include/asm/cpufeature.h        |  3 +-
>  arch/riscv/kernel/traps_misaligned.c       | 71 +++++++++++++++++++++-
>  arch/riscv/kernel/unaligned_access_speed.c |  8 ++-
>  3 files changed, 77 insertions(+), 5 deletions(-)

This causes a regression on platforms where vector misaligned access can
be emulated with OpenSBI (since OpenSBI commit c2acc5e ("lib:
sbi_misaligned_ldst: Add handling of vector load/store"), because this
disables that with FWFT. This means that vector misaligned loads and
stores that were emulated instead get a SIGBUS.

This happens on Sophgo SG2044 and SpacemiT K1. Notably this causes these
platforms to fail Zicclsm which stipulates that misaligned vector memory
accesses succeed if vector instructions are available at all [1].

I'm not very certain why vector emulation support was omitted in this
series. Should we perhaps add the same emulation support to Linux as
well for the sake of these kind of platforms?

Thanks,
Vivian "dramforever" Wang

[1]: https://github.com/riscv/riscv-profiles/issues/58