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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4256af55e61sm138652275e9.20.2024.07.01.00.15.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Jul 2024 00:15:12 -0700 (PDT) Message-ID: <43941f48-9905-4b25-89ef-6ad75bf1a123@rivosinc.com> Date: Mon, 1 Jul 2024 09:15:09 +0200 Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 4/8] RISC-V: Check Zicclsm to set unaligned access speed To: Charlie Jenkins , Conor Dooley Cc: Jesse Taube , linux-riscv@lists.infradead.org, Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Rob Herring , Krzysztof Kozlowski , Evan Green , Andrew Jones , Xiao Wang , Andy Chiu , Eric Biggers , Greentime Hu , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Heiko Stuebner , Costa Shulyupin , Andrew Morton , Baoquan He , Anup Patel , Zong Li , Sami Tolvanen , Ben Dooks , Alexandre Ghiti , "Gustavo A. R. Silva" , Erick Archer , Joel Granados , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20240625005001.37901-1-jesse@rivosinc.com> <20240625005001.37901-5-jesse@rivosinc.com> <20240626-march-abreast-83414e844250@spud> Content-Language: en-US From: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 27/06/2024 23:20, Charlie Jenkins wrote: > On Wed, Jun 26, 2024 at 03:39:14PM +0100, Conor Dooley wrote: >> On Mon, Jun 24, 2024 at 08:49:57PM -0400, Jesse Taube wrote: >>> Check for Zicclsm before checking for unaligned access speed. This will >>> greatly reduce the boot up time as finding the access speed is no longer >>> necessary. >>> >>> Signed-off-by: Jesse Taube >>> --- >>> V2 -> V3: >>> - New patch split from previous patch >>> --- >>> arch/riscv/kernel/unaligned_access_speed.c | 26 ++++++++++++++-------- >>> 1 file changed, 17 insertions(+), 9 deletions(-) >>> >>> diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c >>> index a9a6bcb02acf..329fd289b5c8 100644 >>> --- a/arch/riscv/kernel/unaligned_access_speed.c >>> +++ b/arch/riscv/kernel/unaligned_access_speed.c >>> @@ -259,23 +259,31 @@ static int check_unaligned_access_speed_all_cpus(void) >>> kfree(bufs); >>> return 0; >>> } >>> +#else /* CONFIG_RISCV_PROBE_UNALIGNED_ACCESS */ >>> +static int check_unaligned_access_speed_all_cpus(void) >>> +{ >>> + return 0; >>> +} >>> +#endif >>> >>> static int check_unaligned_access_all_cpus(void) >>> { >>> - bool all_cpus_emulated = check_unaligned_access_emulated_all_cpus(); >>> + bool all_cpus_emulated; >>> + int cpu; >>> + >>> + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICCLSM)) { >>> + for_each_online_cpu(cpu) { >>> + per_cpu(misaligned_access_speed, cpu) = RISCV_HWPROBE_MISALIGNED_FAST; >> >> - const: zicclsm >> description: >> The standard Zicclsm extension for misaligned support for all regular >> load and store instructions (including scalar and vector) but not AMOs >> or other specialized forms of memory access. Defined in the >> RISC-V RVA Profiles Specification. >> >> Doesn't, unfortunately, say anywhere there that they're actually fast :( > > Oh no! That is unfortunate that the ISA does not explicitly call that > out, but I think that acceptable. > > If a vendor puts Zicclsm in their isa string, they should expect > software to take advantage of misaligned accesses. FAST is our signal to > tell software that they should emit misaligned accesses. AFAIK, Zicclsm is not even an ISA extension, simply a profile specification which means that only the execution environment which provides the profile support misaligned accesses (cf https://lists.riscv.org/g/tech-profiles/message/56). I don't think we can extrapolate that the misaligned accesses will be fast at all. Thanks, Clément > > This allows for a generic kernel, like the one a distro would compile, to > skip the probing when booting on a system that explicitly called out > that the hardware supports misaligned accesses. > > - Charlie > >> >> Thanks, >> Conor. >> >>> + } >>> + return 0; >>> + } >>> + >>> + all_cpus_emulated = check_unaligned_access_emulated_all_cpus(); >>> >>> if (!all_cpus_emulated) >>> return check_unaligned_access_speed_all_cpus(); >>> >>> return 0; >>> } >>> -#else /* CONFIG_RISCV_PROBE_UNALIGNED_ACCESS */ >>> -static int check_unaligned_access_all_cpus(void) >>> -{ >>> - check_unaligned_access_emulated_all_cpus(); >>> - >>> - return 0; >>> -} >>> -#endif >>> >>> arch_initcall(check_unaligned_access_all_cpus); >>> -- >>> 2.45.2 >>> > >