From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.1 (2015-04-28) on archive.lwn.net X-Spam-Level: X-Spam-Status: No, score=-5.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham autolearn_force=no version=3.4.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by archive.lwn.net (Postfix) with ESMTP id B32CF7D04F for ; Fri, 28 Sep 2018 17:01:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728910AbeI1XZv (ORCPT ); Fri, 28 Sep 2018 19:25:51 -0400 Received: from mga14.intel.com ([192.55.52.115]:7266 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726738AbeI1XZv (ORCPT ); Fri, 28 Sep 2018 19:25:51 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Sep 2018 10:01:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,315,1534834800"; d="scan'208";a="266822787" Received: from 2b52.sc.intel.com ([143.183.136.51]) by fmsmga005.fm.intel.com with ESMTP; 28 Sep 2018 10:01:11 -0700 Message-ID: <459b7c5d85ef57b02985813d59f7dd3f7cc18368.camel@intel.com> Subject: Re: [RFC PATCH v4 01/27] x86/cpufeatures: Add CPUIDs for Control-flow Enforcement Technology (CET) From: Yu-cheng Yu To: Borislav Petkov Cc: x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Cyrill Gorcunov , Dave Hansen , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , "Ravi V. Shankar" , Vedvyas Shanbhogue Date: Fri, 28 Sep 2018 09:56:32 -0700 In-Reply-To: <20180928165118.GD20768@zn.tnic> References: <20180921150351.20898-1-yu-cheng.yu@intel.com> <20180921150351.20898-2-yu-cheng.yu@intel.com> <20180928165118.GD20768@zn.tnic> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.1-2 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-doc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org On Fri, 2018-09-28 at 18:51 +0200, Borislav Petkov wrote: > On Fri, Sep 21, 2018 at 08:03:25AM -0700, Yu-cheng Yu wrote: > > Add CPUIDs for Control-flow Enforcement Technology (CET). > > > > CPUID.(EAX=7,ECX=0):ECX[bit 7] Shadow stack > > CPUID.(EAX=7,ECX=0):EDX[bit 20] Indirect branch tracking > > > > Signed-off-by: Yu-cheng Yu > > --- > > arch/x86/include/asm/cpufeatures.h | 2 ++ > > arch/x86/kernel/cpu/scattered.c | 1 + > > 2 files changed, 3 insertions(+) > > > > diff --git a/arch/x86/include/asm/cpufeatures.h > > b/arch/x86/include/asm/cpufeatures.h > > index 89a048c2faec..fa69651a017e 100644 > > --- a/arch/x86/include/asm/cpufeatures.h > > +++ b/arch/x86/include/asm/cpufeatures.h > > @@ -221,6 +221,7 @@ > > #define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD > > family 0x17 (Zen) */ > > #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF > > workaround PTE inversion */ > > #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */ > > +#define X86_FEATURE_IBT ( 7*32+31) /* Indirect > > Branch Tracking */ > > > > /* Virtualization flags: Linux defined, word 8 */ > > #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR > > Shadow */ > > @@ -321,6 +322,7 @@ > > #define X86_FEATURE_PKU (16*32+ 3) /* Protection > > Keys for Userspace */ > > #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys > > Enable */ > > #define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 > > Vector Bit Manipulation Instructions */ > > +#define X86_FEATURE_SHSTK (16*32+ 7) /* Shadow Stack */ > > #define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New > > Instructions */ > > #define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */ > > #define X86_FEATURE_VPCLMULQDQ (16*32+10) /* Carry-Less > > Multiplication Double Quadword */ > > diff --git a/arch/x86/kernel/cpu/scattered.c > > b/arch/x86/kernel/cpu/scattered.c > > index 772c219b6889..63cbb4d9938e 100644 > > --- a/arch/x86/kernel/cpu/scattered.c > > +++ b/arch/x86/kernel/cpu/scattered.c > > @@ -21,6 +21,7 @@ struct cpuid_bit { > > static const struct cpuid_bit cpuid_bits[] = { > > { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 }, > > { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 }, > > + { X86_FEATURE_IBT, CPUID_EDX, 20, 0x00000007, 0}, > > If you haven't noticed, there's already a separate leaf: > > /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ > > in arch/x86/include/asm/cpufeatures.h > I will change to that one. Thanks! Yu-cheng