From: Paolo Abeni <pabeni@redhat.com>
To: Vadim Fedorenko <vadim.fedorenko@linux.dev>,
Ivan Vecera <ivecera@redhat.com>,
netdev@vger.kernel.org
Cc: Prathosh Satish <Prathosh.Satish@microchip.com>,
Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
Jiri Pirko <jiri@resnulli.us>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Simon Horman <horms@kernel.org>,
Jonathan Corbet <corbet@lwn.net>, Jason Gunthorpe <jgg@ziepe.ca>,
Shannon Nelson <shannon.nelson@amd.com>,
Dave Jiang <dave.jiang@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, Michal Schmidt <mschmidt@redhat.com>,
Petr Oros <poros@redhat.com>
Subject: Re: [PATCH net-next v11 13/14] dpll: zl3073x: Add support to get/set frequency on input pins
Date: Thu, 19 Jun 2025 15:23:31 +0200 [thread overview]
Message-ID: <45b79d7d-dc26-491b-b5e6-c5f5ab210850@redhat.com> (raw)
In-Reply-To: <ba027737-39df-4541-8fea-1c4cf489b43b@linux.dev>
On 6/19/25 2:15 PM, Vadim Fedorenko wrote:
> On 19/06/2025 12:15, Paolo Abeni wrote:
>> On 6/16/25 10:14 PM, Ivan Vecera wrote:
>>> +/**
>>> + * zl3073x_dpll_input_ref_frequency_get - get input reference frequency
>>> + * @zldpll: pointer to zl3073x_dpll
>>> + * @ref_id: reference id
>>> + * @frequency: pointer to variable to store frequency
>>> + *
>>> + * Reads frequency of given input reference.
>>> + *
>>> + * Return: 0 on success, <0 on error
>>> + */
>>> +static int
>>> +zl3073x_dpll_input_ref_frequency_get(struct zl3073x_dpll *zldpll, u8 ref_id,
>>> + u32 *frequency)
>>> +{
>>> + struct zl3073x_dev *zldev = zldpll->dev;
>>> + u16 base, mult, num, denom;
>>> + int rc;
>>> +
>>> + guard(mutex)(&zldev->multiop_lock);
>>> +
>>> + /* Read reference configuration */
>>> + rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD,
>>> + ZL_REG_REF_MB_MASK, BIT(ref_id));
>>> + if (rc)
>>> + return rc;
>>> +
>>> + /* Read registers to compute resulting frequency */
>>> + rc = zl3073x_read_u16(zldev, ZL_REG_REF_FREQ_BASE, &base);
>>> + if (rc)
>>> + return rc;
>>> + rc = zl3073x_read_u16(zldev, ZL_REG_REF_FREQ_MULT, &mult);
>>> + if (rc)
>>> + return rc;
>>> + rc = zl3073x_read_u16(zldev, ZL_REG_REF_RATIO_M, &num);
>>> + if (rc)
>>> + return rc;
>>> + rc = zl3073x_read_u16(zldev, ZL_REG_REF_RATIO_N, &denom);
>>> + if (rc)
>>> + return rc;
>>> +
>>> + /* Sanity check that HW has not returned zero denominator */
>>> + if (!denom) {
>>> + dev_err(zldev->dev,
>>> + "Zero divisor for ref %u frequency got from device\n",
>>> + ref_id);
>>> + return -EINVAL;
>>> + }
>>> +
>>> + /* Compute the frequency */
>>> + *frequency = base * mult * num / denom;
>>
>> As base, mult, num and denom are u16, the above looks like integer
>> overflow prone.
>>
>> I think you should explicitly cast to u64, and possibly use a u64 frequency.
>
> I might be a good idea to use mul_u64_u32_div together with mul_u32_u32?
> These macroses will take care of overflow on 32bit platforms as well.
I guess such macros will work, but u64 is available on 32bits platform
as well - and possibly simpler/more readable.
/P
next prev parent reply other threads:[~2025-06-19 13:23 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-16 20:13 [PATCH net-next v11 00/14] Add Microchip ZL3073x support (part 1) Ivan Vecera
2025-06-16 20:13 ` [PATCH net-next v11 01/14] dt-bindings: dpll: Add DPLL device and pin Ivan Vecera
2025-06-16 20:13 ` [PATCH net-next v11 02/14] dt-bindings: dpll: Add support for Microchip Azurite chip family Ivan Vecera
2025-06-16 20:13 ` [PATCH net-next v11 03/14] dpll: Add basic Microchip ZL3073x support Ivan Vecera
2025-06-18 8:56 ` Jonathan Cameron
2025-06-19 11:43 ` Paolo Abeni
2025-06-20 17:05 ` Ivan Vecera
2025-06-29 18:59 ` Ivan Vecera
2025-06-16 20:13 ` [PATCH net-next v11 04/14] dpll: zl3073x: Add support for devlink device info Ivan Vecera
2025-06-16 20:13 ` [PATCH net-next v11 05/14] dpll: zl3073x: Protect operations requiring multiple register accesses Ivan Vecera
2025-06-16 20:13 ` [PATCH net-next v11 06/14] dpll: zl3073x: Fetch invariants during probe Ivan Vecera
2025-06-16 20:13 ` [PATCH net-next v11 07/14] dpll: zl3073x: Add clock_id field Ivan Vecera
2025-06-16 20:13 ` [PATCH net-next v11 08/14] dpll: zl3073x: Read DPLL types and pin properties from system firmware Ivan Vecera
2025-06-16 20:13 ` [PATCH net-next v11 09/14] dpll: zl3073x: Register DPLL devices and pins Ivan Vecera
2025-06-16 20:14 ` [PATCH net-next v11 10/14] dpll: zl3073x: Implement input pin selection in manual mode Ivan Vecera
2025-06-16 20:14 ` [PATCH net-next v11 11/14] dpll: zl3073x: Add support to get/set priority on input pins Ivan Vecera
2025-06-16 20:14 ` [PATCH net-next v11 12/14] dpll: zl3073x: Implement input pin state setting in automatic mode Ivan Vecera
2025-06-16 20:14 ` [PATCH net-next v11 13/14] dpll: zl3073x: Add support to get/set frequency on input pins Ivan Vecera
2025-06-19 11:15 ` Paolo Abeni
2025-06-19 12:15 ` Vadim Fedorenko
2025-06-19 13:23 ` Paolo Abeni [this message]
2025-06-29 19:01 ` Ivan Vecera
2025-06-16 20:14 ` [PATCH net-next v11 14/14] dpll: zl3073x: Add support to get/set frequency on output pins Ivan Vecera
2025-06-19 11:40 ` Paolo Abeni
2025-06-29 19:04 ` Ivan Vecera
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