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Mon, 15 Sep 2025 15:46:56 GMT Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8747F58052; Mon, 15 Sep 2025 15:46:56 +0000 (GMT) Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 77CF458056; Mon, 15 Sep 2025 15:46:54 +0000 (GMT) Received: from [9.111.35.47] (unknown [9.111.35.47]) by smtpav04.dal12v.mail.ibm.com (Postfix) with ESMTP; Mon, 15 Sep 2025 15:46:54 +0000 (GMT) Message-ID: <4fa71778403c8025a85f30dd8a7dcf5bc9a4eaf9.camel@linux.ibm.com> Subject: Re: [PATCH v2 4/4] Documentation: PCI: Tidy error recovery doc's PCIe nomenclature From: Niklas Schnelle To: Lukas Wunner , Bjorn Helgaas , Jonathan Corbet Cc: Terry Bowman , Ilpo Jarvinen , Sathyanarayanan Kuppuswamy , Linas Vepstas , Mahesh J Salgaonkar , Oliver OHalloran , linuxppc-dev@lists.ozlabs.org, linux-pci@vger.kernel.org, linux-doc@vger.kernel.org, Brian Norris Date: Mon, 15 Sep 2025 17:46:53 +0200 In-Reply-To: References: Autocrypt: addr=schnelle@linux.ibm.com; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2 (3.56.2-2.fc42) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTEzMDAxMCBTYWx0ZWRfX14HVU/Ad9H+s dIMMkG8ig5O2lYnBuhe29UZ6F+0hs+ERgs4O5n2QAuFIsbuzoyCmXOjowH6kf89mU9CDjy27SF1 4OJUqST7Hmh7pB6YD4SPRef98HzUoBj+faVEEWeKyKnyDhJTXoWLXBOE6yXM2kUKUwmKISxfv1X HJo9nIXgdheUKAz8gvh6+xfa/1Xhs8RKjKgvgWJkiolKHxxvK/GqdfNCGQ2b5OlGcaWGOSPM5nZ 84dstqf+fCAku3f4XO/1MEKzL+P9fLE/WjLV9sHrB5bF3X/SfnJv4IISHzcw2hCq4Y8Zz9aWBf2 XO6D1eJufvs2CV/4fDJtMFRGsJ8aA3xL0flXHDCHAhlzOpD5Dk52z37amULIDES2R63NGOrwFRM /9Ya7jUA X-Proofpoint-ORIG-GUID: 5J-H0mxm43hN5dGBn6qJ-0K5DhG9kypG X-Authority-Analysis: v=2.4 cv=euPfzppX c=1 sm=1 tr=0 ts=68c834f2 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=cm27Pg_UAAAA:8 a=VnNF1IyMAAAA:8 a=XEWlu9VqNwFSst1M3Z8A:9 a=QEXdDO2ut3YA:10 X-Proofpoint-GUID: 5-0ZgXorGEHd5_Td74dNKWHL9i0MXvvs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-15_06,2025-09-12_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 phishscore=0 suspectscore=0 spamscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509130010 On Mon, 2025-09-15 at 15:50 +0200, Lukas Wunner wrote: > Commit 11502feab423 ("Documentation: PCI: Tidy AER documentation") > replaced the terms "PCI-E", "PCI-Express" and "PCI Express" with "PCIe" > in the AER documentation. >=20 > Do the same in the documentation on PCI error recovery. While at it, > add a missing period and a missing blank. >=20 > Signed-off-by: Lukas Wunner > Reviewed-by: Brian Norris > --- > Documentation/PCI/pci-error-recovery.rst | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) >=20 > diff --git a/Documentation/PCI/pci-error-recovery.rst b/Documentation/PCI= /pci-error-recovery.rst > index 9e1e2f2a13fa..5df481ac6193 100644 > --- a/Documentation/PCI/pci-error-recovery.rst > +++ b/Documentation/PCI/pci-error-recovery.rst > @@ -13,7 +13,7 @@ PCI Error Recovery > Many PCI bus controllers are able to detect a variety of hardware > PCI errors on the bus, such as parity errors on the data and address > buses, as well as SERR and PERR errors. Some of the more advanced > -chipsets are able to deal with these errors; these include PCI-E chipset= s, > +chipsets are able to deal with these errors; these include PCIe chipsets= , > and the PCI-host bridges found on IBM Power4, Power5 and Power6-based > pSeries boxes. A typical action taken is to disconnect the affected devi= ce, > halting all I/O to it. The goal of a disconnection is to avoid system > @@ -206,7 +206,7 @@ reset or some such, but not restart operations. This = callback is made if > all drivers on a segment agree that they can try to recover and if no au= tomatic > link reset was performed by the HW. If the platform can't just re-enable= IOs > without a slot reset or a link reset, it will not call this callback, an= d > -instead will have gone directly to STEP 3 (Link Reset) or STEP 4 (Slot R= eset) > +instead will have gone directly to STEP 3 (Link Reset) or STEP 4 (Slot R= eset). > =20 > .. note:: > =20 > @@ -259,14 +259,14 @@ The driver should return one of the following resul= t codes: > =20 > The next step taken depends on the results returned by the drivers. > If all drivers returned PCI_ERS_RESULT_RECOVERED, then the platform > -proceeds to either STEP3 (Link Reset) or to STEP 5 (Resume Operations). > +proceeds to either STEP 3 (Link Reset) or to STEP 5 (Resume Operations). > =20 > If any driver returned PCI_ERS_RESULT_NEED_RESET, then the platform > proceeds to STEP 4 (Slot Reset) > =20 > STEP 3: Link Reset > ------------------ > -The platform resets the link. This is a PCI-Express specific step > +The platform resets the link. This is a PCIe specific step > and is done whenever a fatal error has been detected that can be > "solved" by resetting the link. > =20 > @@ -288,13 +288,13 @@ that is equivalent to what it would be after a fres= h system > power-on followed by power-on BIOS/system firmware initialization. > Soft reset is also known as hot-reset. > =20 > -Powerpc fundamental reset is supported by PCI Express cards only > +Powerpc fundamental reset is supported by PCIe cards only > and results in device's state machines, hardware logic, port states and > configuration registers to initialize to their default conditions. > =20 > For most PCI devices, a soft reset will be sufficient for recovery. > Optional fundamental reset is provided to support a limited number > -of PCI Express devices for which a soft reset is not sufficient > +of PCIe devices for which a soft reset is not sufficient > for recovery. > =20 > If the platform supports PCI hotplug, then the reset might be > @@ -338,7 +338,7 @@ Result codes: > - PCI_ERS_RESULT_DISCONNECT > Same as above. > =20 > -Drivers for PCI Express cards that require a fundamental reset must > +Drivers for PCIe cards that require a fundamental reset must > set the needs_freset bit in the pci_dev structure in their probe functio= n. > For example, the QLogic qla2xxx driver sets the needs_freset bit for cer= tain > PCI card types:: Thanks for the bringing this in sync. Reviewed-by: Niklas Schnelle