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Wysocki" , Jonathan Corbet , linux-cxl@vger.kernel.org, Tony Luck , Borislav Petkov , Hanjun Guo , Mauro Carvalho Chehab , Shuai Xue , Len Brown , Ira Weiny , Li Ming , Shuah Khan , Ben Cheatham , Richard Cheng , Robert Richter , linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260803221810.3685703-1-terry.bowman@amd.com> <20260803221810.3685703-3-terry.bowman@amd.com> Content-Language: en-US From: "Bowman, Terry" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: PH0PR07CA0084.namprd07.prod.outlook.com (2603:10b6:510:f::29) To CH8PR12MB9766.namprd12.prod.outlook.com (2603:10b6:610:2b6::10) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH8PR12MB9766:EE_|DS1PR12MB999188:EE_ X-MS-Office365-Filtering-Correlation-Id: 7f5b12ed-13e7-465f-c4f9-08df0e8d3d89 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|23010399003|7416014|376014|366016|10067099003|5023799004|11063799006|4143699003|56012099006|22082099003|18002099003; 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I'd be > grateful if you could take a look: > > On Sun, Aug 09, 2026 at 05:57:23PM +0200, Lukas Wunner wrote: >> Am I missing something? Is a scenario ever conceivable where the RCEC >> receives a message with different severity than what is inferred from >> the registers by cxl_rch_get_aer_severity()? > [...] >> These so-called Advisory Non-Fatal Errors set one bit in the Correctable >> Error Status Register (Advisory Non-Fatal Error Status, bit 13) and >> additionally one or more bits in the Uncorrectable Error Status Register >> (see the commit for details). >> >> cxl_rch_get_aer_severity() is not able to cope with such errors and >> will incorrectly infer that the severity is AER_NONFATAL. >> >> Now I *think* this is not a problem because Advisory Non-Fatal Errors >> are masked by default and the commit only unmasks them on regular PCI >> devices, not in the RCRB of a CXL device. Only once bit 13 in the >> Correctable Error Mask Register is cleared in the RCRB will >> cxl_rch_get_aer_severity() fail. Right? > > Thanks, > > Lukas Hi Lukas, I’m sorry for missing your August 9 reply. Thanks for pointing out the issue with CE and UCE errors reported simultaneously. I agree this is a problem and have addressed it in v20. In v20 I remove the unused `cxl_rch_get_aer_severity()` helper, take a snapshot of the AER registers before calling `pci_print_aer()`, and now handle the CE and UCE parts in separate blocks. The UCE status is logged unconditionally, which prevents a fatal record from being lost under the advisory‑non‑fatal path. These changes directly address the scenario you raised for v19 and also cover any other situation where a CE and a UCE are co‑logged. The patch is here: (v20 3/9). Jonathan added a comment looking for your feedback on if the issue should be solved by changing pci_print_aer() to be non-destructive instead. It is here: https://lore.kernel.org/linux-cxl/20260908020608.56e8c443@jic23-huawei/ - Terry