Re: [PATCH v6 0/8] cxl: support CXL memory RAS features

[Dan Williams <dan.j.williams@intel.com>]

shiju.jose@ wrote:
> From: Shiju Jose <shiju.jose@huawei.com>
> 
> Support for CXL memory EDAC features: patrol scrub, ECS, soft-PPR and
> memory sparing.
> 
> Detailed history of the complete EDAC series with CXL EDAC patches
> up to V20 [1] and this CXL specific series had separated from V20 of
> the above series.
> 
> The series is based on [2] v6.15-rc4 (based on comment from Dave
> in the thread [4]).
> 
> Also applied(no conflicts) and tested on cxl.git [3] branch: next
> 
> 1. https://lore.kernel.org/linux-cxl/20250212143654.1893-1-shiju.jose@huawei.com/
> 2. https://github.com/torvalds/linux.git
> 3. https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git
> 4. https://lore.kernel.org/all/d83a83d1-37e7-4192-913f-243098f679e3@intel.com/
> 
> Userspace code for CXL memory repair features [5] and
> sample boot-script for CXL memory repair [6].
> 
> [5]: https://lore.kernel.org/lkml/20250207143028.1865-1-shiju.jose@huawei.com/
> [6]: https://lore.kernel.org/lkml/20250207143028.1865-5-shiju.jose@huawei.com/

All of my prior review comments are addressed, the maze of type-unsafe
callbacks gives me pause, but not disqualifying since it is all
self-contained out of the way in drivers/cxl/core/edac.c

For the series you can add:

Acked-by: Dan Williams <dan.j.williams@intel.com>