Re: [PATCH v3 3/3] Documentation/driver-api/cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement

[<dan.j.williams@intel.com>]

Robert Richter wrote:
> This adds a convention document for the following patch series:
> 
>  cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement
> 
> Version 7 and later:
> 
>  https://lore.kernel.org/linux-cxl/20251114213931.30754-1-rrichter@amd.com/
> 
> Link: https://lore.kernel.org/linux-cxl/20251114213931.30754-1-rrichter@amd.com/
> Reviewed-by: Gregory Price <gourry@gourry.net>
> Signed-off-by: Robert Richter <rrichter@amd.com>
> ---
> v3:
>  * updated link in descriptions and add Link: tag (Jonathan Cameron),
>  * clarified CFMWS and HPA range description (Jonathan Cameron),
>  * use 80 chars line limit (Jonathan Cameron),
>  * added block diagram to illustrate the example address mappings (Dave),
> v2:
>  * updated sob-chain,
>  * spell fix in patch description (Randy),
>  * made small changes as suggested by Randy,
>  * Removed include:: <isonum.txt> line (Jon).
> Signed-off-by: Robert Richter <rrichter@amd.com>
> ---
>  Documentation/driver-api/cxl/conventions.rst  |   1 +
>  .../driver-api/cxl/conventions/cxl-atl.rst    | 205 ++++++++++++++++++
>  2 files changed, 206 insertions(+)
>  create mode 100644 Documentation/driver-api/cxl/conventions/cxl-atl.rst
> 
> diff --git a/Documentation/driver-api/cxl/conventions.rst b/Documentation/driver-api/cxl/conventions.rst
> index 9267a697b2fe..0d2e07279ad9 100644
> --- a/Documentation/driver-api/cxl/conventions.rst
> +++ b/Documentation/driver-api/cxl/conventions.rst
[..]
> +Detailed Description of the Change
> +----------------------------------
> +
> +Add the following paragraph in 8.2.4.20 CXL HDM Decoder Capability Structure of
> +the specification [#cxl-spec-3.2]_ to the end:
> +
> +"A device may use a different HPA space that is not common to other components
> +of the host domain. The platform is responsible for address translation when
> +crossing HPA spaces. The OSPM must determine the interleaving configuration and
> +perform address translation to HPA ranges of the HDM decoders as needed. The
> +translation mechanism is host-specific and implementation dependent."

Thanks for this Robert. The only comment I would is to include the GUID
and calling convention details in this documentation proposal. I.e. make
it a common definition / generic concept such that someone else could
conceivably reuse the same GUID.

I.e. AMD is just the first user of "Normalized address mode", and this
contribution is defined for reuse outside of Zen5. Not that I expect
anyone else *would* use this, but I do not see how anyone could write an
implementation from the above limited addition to the CXL specification.

So extend the existing ACPI method calls in the spec beyong CXL _OSC and
and ACPI0017 QoS-class _DSM, to include this new _DSM definition.

With that detail fixed up you can add:

Acked-by: Dan Williams <dan.j.williams@intel.com>