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From: "Dan Williams (nvidia)" <djbw@kernel.org>
To: Manish Honap <mhonap@nvidia.com>,  Alex Williamson <alex@shazbot.org>
Cc: "djbw@kernel.org" <djbw@kernel.org>,
	 "jgg@ziepe.ca" <jgg@ziepe.ca>,
	 "jic23@kernel.org" <jic23@kernel.org>,
	 "dave.jiang@intel.com" <dave.jiang@intel.com>,
	 Ankit Agrawal <ankita@nvidia.com>,
	 "alejandro.lucero-palau@amd.com"
	<alejandro.lucero-palau@amd.com>,
	 "alison.schofield@intel.com" <alison.schofield@intel.com>,
	 "dave@stgolabs.net" <dave@stgolabs.net>,
	 "dmatlack@google.com" <dmatlack@google.com>,
	 "gourry@gourry.net" <gourry@gourry.net>,
	 "ira.weiny@intel.com" <ira.weiny@intel.com>,
	 Neo Jia <cjia@nvidia.com>,  Krishnakant Jaju <kjaju@nvidia.com>,
	 Vikram Sethi <vsethi@nvidia.com>,  Zhi Wang <zhiw@nvidia.com>,
	 "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	 "linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
	 "linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
	 "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	 "linux-kselftest@vger.kernel.org"
	<linux-kselftest@vger.kernel.org>,
	 Manish Honap <mhonap@nvidia.com>
Subject: RE: [PATCH v3 05/11] vfio: UAPI for CXL Type-2 device passthrough
Date: Mon, 13 Jul 2026 14:14:20 -0700	[thread overview]
Message-ID: <6a55552c98a82_35cf3310082@djbw-dev.notmuch> (raw)
In-Reply-To: <IA1PR12MB9030E175587B09CEA7A4D90FBDFA2@IA1PR12MB9030.namprd12.prod.outlook.com>

Manish Honap wrote:
> > -----Original Message-----
> > From: Alex Williamson <alex@shazbot.org>
> > Sent: 11 July 2026 03:53
> > To: Manish Honap <mhonap@nvidia.com>
> > Cc: djbw@kernel.org; jgg@ziepe.ca; jic23@kernel.org;
> > dave.jiang@intel.com; Ankit Agrawal <ankita@nvidia.com>;
> > alejandro.lucero-palau@amd.com; alison.schofield@intel.com;
> > dave@stgolabs.net; dmatlack@google.com; gourry@gourry.net;
> > ira.weiny@intel.com; Neo Jia <cjia@nvidia.com>; Krishnakant Jaju
> > <kjaju@nvidia.com>; Vikram Sethi <vsethi@nvidia.com>; Zhi Wang
> > <zhiw@nvidia.com>; kvm@vger.kernel.org; linux-cxl@vger.kernel.org;
> > linux-doc@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
> > kselftest@vger.kernel.org; alex@shazbot.org
> > Subject: Re: [PATCH v3 05/11] vfio: UAPI for CXL Type-2 device
> > passthrough
> > 
[..]
> > 
> > On Thu, 25 Jun 2026 22:24:01 +0530
> > <mhonap@nvidia.com> wrote:
> > > diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h
> > > index 5de618a3a5ee..3707d53c4de5 100644
> > > --- a/include/uapi/linux/vfio.h
> > > +++ b/include/uapi/linux/vfio.h
> > > @@ -215,6 +215,7 @@ struct vfio_device_info {
> > >  #define VFIO_DEVICE_FLAGS_FSL_MC (1 << 6)    /* vfio-fsl-mc device */
> > >  #define VFIO_DEVICE_FLAGS_CAPS       (1 << 7)        /* Info supports
> > caps */
> > >  #define VFIO_DEVICE_FLAGS_CDX        (1 << 8)        /* vfio-cdx
> > device */
> > > +#define VFIO_DEVICE_FLAGS_CXL        (1 << 9)        /* vfio-cxl
> > Type-2 device */
> > 
> > Would we define a different flag for type-1/3 if we ever found a need to
> > expose them through vfio?
> 
> Yes. The current flag is named VFIO_DEVICE_FLAGS_CXL and refers to
> Type-2 specifically. If Type-1 or Type-3 support is added later, a
> separate flag (or a VFIO_DEVICE_INFO_CAP sub-type field) would
> distinguish them. I can rename it VFIO_DEVICE_FLAGS_CXL_TYPE2 now if
> that is preferable; please advise.

The CXL specification itself has deprecated the "Type" names because
they are ambiguous. For example, you can have a "Type-3" device that
supports "device memory (HDM-DB)", Type-2 is a superset of Type-1 in
many cases, etc.

This flag will never be able to capture a coherent / standard set of
device capabilities. It can really only be a plain "CXL" flag with
an implementation that is ready for the superset of capabilities:
CXL.cache, HDM-H (host-only memory expansion), HDM-D (legacy device
memory), HDM-DB (device memory via device cache management
back-invalidate).

I think the HDM-{H,D,DB} difference are not relevant to VFIO, it is all
just CXL HDM.

The capabilities that may need a different VFIO implementation model are
interleaved devices and maybe dynamic capacity devices, but that is not
a type designation.

[..]
> > Does that leave this device level capability describing the device as
> > type-2 (by existence), with only a flags field to declare HDM as
> > firmware committed, for future compatibility should we support non-fw
> > committed?  Thanks,
> > 
> > Alex
> 
> Yes, I will shape the v4 in this direction. The device-level CAP_CXL
> shrinks to "this is a CXL device" (by existence) plus a flags field whose
> only defined bit today is HOST_FIRMWARE_COMMITTED, leaving
> room for a future non-fw-committed mode. Everything else moves to region
> caps. Thanks for this suggestion.

How can VFIO discern if the HDM is host firwmare committed? If
devm_cxl_probe_mem() grows to auto-activate unmapped capacity rather
than finds firmware committed decoders, can VFIO even tell the
difference?

  parent reply	other threads:[~2026-07-13 21:14 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-25 16:53 [PATCH v3 00/11] vfio/pci: Add CXL Type-2 device passthrough support mhonap
2026-06-25 16:53 ` [PATCH v3 01/11] cxl: Add cxl_get_hdm_info() helper for HDM decoder metadata mhonap
2026-07-10  1:00   ` Dan Williams (nvidia)
2026-07-13 16:44     ` Manish Honap
2026-06-25 16:53 ` [PATCH v3 02/11] cxl: Split cxl_await_range_active() from media-ready wait mhonap
2026-06-25 16:53 ` [PATCH v3 03/11] cxl: Record BIR and BAR offset in cxl_register_map mhonap
2026-06-25 16:54 ` [PATCH v3 04/11] cxl: Move component/HDM register defines to uapi/cxl/cxl_regs.h mhonap
2026-06-25 16:54 ` [PATCH v3 05/11] vfio: UAPI for CXL Type-2 device passthrough mhonap
2026-07-10 22:23   ` Alex Williamson
2026-07-13 16:44     ` Manish Honap
2026-07-13 17:40       ` Manish Honap
2026-07-13 21:14       ` Dan Williams (nvidia) [this message]
2026-07-13 23:37       ` Alex Williamson
2026-06-25 16:54 ` [PATCH v3 06/11] cxl: Add register-virtualization helpers for vfio Type-2 passthrough mhonap
2026-07-10 21:56   ` Dan Williams (nvidia)
2026-07-13 16:46     ` Manish Honap
2026-06-25 16:54 ` [PATCH v3 07/11] vfio/pci: Add CONFIG_VFIO_PCI_CXL with bind-time CXL Type-2 acquisition mhonap
2026-07-10 22:23   ` Alex Williamson
2026-07-13 16:48     ` Manish Honap
2026-07-14  4:32       ` Dan Williams (nvidia)
2026-06-25 16:54 ` [PATCH v3 08/11] vfio/pci/cxl: Add HDM + COMP_REGS regions and DVSEC clipping shim mhonap
2026-07-10 22:09   ` Dan Williams (nvidia)
2026-07-13 16:48     ` Manish Honap
2026-07-10 22:23   ` Alex Williamson
2026-07-13 16:48     ` Manish Honap
2026-06-25 16:54 ` [PATCH v3 09/11] selftests/vfio: Add CXL Type-2 device passthrough smoke test mhonap
2026-06-25 16:54 ` [PATCH v3 10/11] docs: vfio-pci: Document CXL Type-2 device passthrough mhonap
2026-06-25 16:54 ` [PATCH v3 11/11] vfio/pci: Provide opt-out for CXL Type-2 extensions mhonap
2026-06-26  9:16 ` [PATCH v3 00/11] vfio/pci: Add CXL Type-2 device passthrough support Richard Cheng
2026-07-13 16:44   ` Manish Honap
2026-07-10 16:26 ` Dave Jiang
2026-07-13 16:43   ` Manish Honap

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