From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B269FC7EE23 for ; Thu, 1 Jun 2023 14:49:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233035AbjFAOtV (ORCPT ); Thu, 1 Jun 2023 10:49:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229498AbjFAOtU (ORCPT ); Thu, 1 Jun 2023 10:49:20 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 6C959E2; Thu, 1 Jun 2023 07:49:19 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8FC2D1063; Thu, 1 Jun 2023 07:50:04 -0700 (PDT) Received: from [10.57.84.85] (unknown [10.57.84.85]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 53D493F663; Thu, 1 Jun 2023 07:49:17 -0700 (PDT) Message-ID: <7269d265-154b-e79a-2622-287e149d85ad@arm.com> Date: Thu, 1 Jun 2023 15:49:13 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH v2 1/5] perf: arm_cspmu: Support 32-bit accesses to 64-bit registers Content-Language: en-GB To: Ilkka Koskinen , Jonathan Corbet , Will Deacon , Mark Rutland , Besar Wicaksono , Suzuki K Poulose Cc: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20230601030144.3458136-1-ilkka@os.amperecomputing.com> <20230601030144.3458136-2-ilkka@os.amperecomputing.com> From: Robin Murphy In-Reply-To: <20230601030144.3458136-2-ilkka@os.amperecomputing.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org On 2023-06-01 04:01, Ilkka Koskinen wrote: > Split the 64-bit register accesses if 64-bit access is not supported > by the PMU. > > Signed-off-by: Ilkka Koskinen > --- > drivers/perf/arm_cspmu/arm_cspmu.c | 8 ++++++-- > drivers/perf/arm_cspmu/arm_cspmu.h | 1 + > 2 files changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/arm_cspmu.c > index a3f1c410b417..88547a2b73e6 100644 > --- a/drivers/perf/arm_cspmu/arm_cspmu.c > +++ b/drivers/perf/arm_cspmu/arm_cspmu.c > @@ -701,8 +701,12 @@ static void arm_cspmu_write_counter(struct perf_event *event, u64 val) > > if (use_64b_counter_reg(cspmu)) { > offset = counter_offset(sizeof(u64), event->hw.idx); > - > - writeq(val, cspmu->base1 + offset); > + if (!cspmu->impl.split_64bit_access) { Could we not just hang this off the 64-bit atomicity property to match the read path? It doesn't seem like there's much benefit in micro-optimising for whether the interconnect splits 64-bit accesses into 32-bit bursts vs. just not accepting them at all. > + writeq(val, cspmu->base1 + offset); > + } else { > + writel(lower_32_bits(val), cspmu->base1 + offset); > + writel(upper_32_bits(val), cspmu->base1 + offset + 4); lo_hi_writeq() - the header's already included for 32-bit build coverage, so we may as well put it to use :) Thanks, Robin. > + } > } else { > offset = counter_offset(sizeof(u32), event->hw.idx); > > diff --git a/drivers/perf/arm_cspmu/arm_cspmu.h b/drivers/perf/arm_cspmu/arm_cspmu.h > index 51323b175a4a..c0412cf2bd97 100644 > --- a/drivers/perf/arm_cspmu/arm_cspmu.h > +++ b/drivers/perf/arm_cspmu/arm_cspmu.h > @@ -110,6 +110,7 @@ struct arm_cspmu_impl_ops { > /* Vendor/implementer descriptor. */ > struct arm_cspmu_impl { > u32 pmiidr; > + bool split_64bit_access; > struct arm_cspmu_impl_ops ops; > void *ctx; > };