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[1.41.240.65]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b422babfbbdsm28366124a12.35.2025.08.13.16.07.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Aug 2025 16:08:06 -0700 (PDT) Message-ID: <7aa7035f-d2c4-4c00-bc46-2e98d4c2641f@oss.qualcomm.com> Date: Thu, 14 Aug 2025 09:07:58 +1000 Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 10/11] qcomtee: enable TEE_IOC_SHM_ALLOC ioctl To: Konrad Dybcio , Jens Wiklander , Sumit Garg , Bjorn Andersson , Konrad Dybcio , Bartosz Golaszewski , Apurupa Pattapu , Kees Cook , "Gustavo A. R. Silva" , Sumit Semwal , =?UTF-8?Q?Christian_K=C3=B6nig?= Cc: Harshal Dev , linux-arm-msm@vger.kernel.org, op-tee@lists.trustedfirmware.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, dri-devel@lists.freedesktop.org, linaro-mm-sig@lists.linaro.org, linux-doc@vger.kernel.org, Neil Armstrong , Sumit Garg References: <20250812-qcom-tee-using-tee-ss-without-mem-obj-v7-0-ce7a1a774803@oss.qualcomm.com> <20250812-qcom-tee-using-tee-ss-without-mem-obj-v7-10-ce7a1a774803@oss.qualcomm.com> <3ec0a8d0-7900-45bd-b0d3-90ee8ca7730c@oss.qualcomm.com> Content-Language: en-US From: Amirreza Zarrabi In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=IuYecK/g c=1 sm=1 tr=0 ts=689d1ad8 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=hi51d+lTLNy/RbqRqnOomQ==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=AwBIn8DhAZiLWRgty54A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 0D49YDAsDK8liiZva2rl4sSMYtCexPAV X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA5MDAyNSBTYWx0ZWRfXy8mK82Yqd9fy X8cDSFFv6QLxvBSDK3JfGd4g10e16kZlTQQY3Dhalw5gOotuu3+CCAeVQrZArLNpCTqsMmJxMuK LOpzn78S3q/tsEORfaY6If96cz+yRwDsQ97damONQFqKYCifxvNWXAx0ElEUKLuVTcUf4exsYLu vpihfVYI0U6AvTjWiX/sGb5v/jpzZtfu75QrX+9REcC8p+tYgxYv+7LuoP9f5Dik3hzunJXw6Rr 3dMO6OZu2Xa4Te9o6WhK+YRWrj6t590IvYR/R08lFCLKJN1tQq0xyj8T4BpTlzU/qCqTXzQk7X7 WCt/QNeooxU9uttAZ3qCdEhedoMbZ32+nJhRwyayCxp+0qtHSIupe0/IMzbmFdAne7il4a1pHxL 65wI/SP0 X-Proofpoint-GUID: 0D49YDAsDK8liiZva2rl4sSMYtCexPAV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-13_02,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 spamscore=0 priorityscore=1501 adultscore=0 clxscore=1015 phishscore=0 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508090025 On 8/14/2025 8:49 AM, Konrad Dybcio wrote: > On 8/14/25 12:24 AM, Amirreza Zarrabi wrote: >> >> >> On 8/13/2025 8:00 PM, Konrad Dybcio wrote: >>> On 8/13/25 2:35 AM, Amirreza Zarrabi wrote: >>>> Enable userspace to allocate shared memory with QTEE. Since >>>> QTEE handles shared memory as object, a wrapper is implemented >>>> to represent tee_shm as an object. The shared memory identifier, >>>> obtained through TEE_IOC_SHM_ALLOC, is transferred to the driver using >>>> TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF_INPUT/OUTPUT. >>>> >>>> Tested-by: Neil Armstrong >>>> Acked-by: Sumit Garg >>>> Tested-by: Harshal Dev >>>> Signed-off-by: Amirreza Zarrabi >>>> --- >>> >>> [...] >>> >>>> +/* Mapping information format as expected by QTEE. */ >>>> +struct qcomtee_mapping_info { >>>> + u64 paddr; >>>> + u64 len; >>>> + u32 perms; >>>> +} __packed; >>> >>> Please use types with explicit endianness, e.g. __le32. I'm assuming >>> TZ will always be little-endian, regardless of the host OS >>> >> >> I'm not entirely sure how this point is relevant. As I understand it, >> the core that populates this struct is the same one that accesses it in TZ. >> Your argument would absolutely make sense if the host and TZ were operating >> on different cores with distinct architectures -- such as one being >> little-endian and the other big-endian, which is not the case. > > CONFIG_CPU_BIG_ENDIAN=y exists on arm64 > > Konrad That’s not what I meant. I understand we have this config value, but the argument is whether, in an SMP system, we expect one core to operate in little-endian mode while another operates in big-endian mode. I do not believe that is the case. Then it becomes irrelevant. Amir