From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00C335CB8; Tue, 7 Jan 2025 13:42:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736257338; cv=none; b=O2sclIFCOJ5t0X5TZ8MaAd1fAoBProG8TOzcjFeT+MymNOtZLvQ2NcehW5SWQdBWLikbU8KdJV+S57A/KqbUSq91JZGikM/lGjkiXmdZCaWyac6tqDuo4Vc3tXmK7qO13ql1F9/Y/oOu1Iu9lrp/9fdsAe1Uoo2pH6ecASfmwY8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736257338; c=relaxed/simple; bh=W7FS2V/XkDChOIfQqxynnw3YZaJOtH2JQmXtylUSxXY=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=rmt9jnfGF/KAq6Ia6Jy0jdkzPdJ2g1UXdFaahJQQOTZuSPN0fcgx/kTLxf29hmnaLVAuFpv8GRNHmWsCu3xp6clAm5uwlqWU5FSgxNXTTaUXyGe6IQ6mdJzKzMMxL+Bgam7vlkZ3Xsk2dpeFqPg1cI7l5vdVAeJYc6pnUljvc7A= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=A0mB0N9e; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="A0mB0N9e" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 726BFC4CED6; Tue, 7 Jan 2025 13:42:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736257337; bh=W7FS2V/XkDChOIfQqxynnw3YZaJOtH2JQmXtylUSxXY=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=A0mB0N9eznEDMh6SASE8Lr0SGe5+idZsUgQJZZkibDFhq3Hg1wduxD4ZckNR2V6Cu hGmM3GPhwmAbRb6wHVS7XfVssbkBzyiXbAq4Pp/K9sFbahVx3Z28Ap3W/wLU3ni7VZ f8TaskApgH9GmjR9Qr7nzYTuTlcchZYTWAdZXUvg4bCNeCqMpl0YGDlSUVSXgDjtEi JV1lhjDJANf4CF08/aLPg6kPUsViujSXEOycWti1TKp5M3WA2zltgfEzDYN1O2qd3p bsE2cjJpGTiVxzmI0UTj0AUm+awmFWl+0ztJDg7ecJfOnh5mlhWdpC3FddXoI25sUX l3yDyK97TjUHA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tV9qZ-009ncW-6K; Tue, 07 Jan 2025 13:42:15 +0000 Date: Tue, 07 Jan 2025 13:42:09 +0000 Message-ID: <8634huyc3y.wl-maz@kernel.org> From: Marc Zyngier To: Rob Herring , Catalin Marinas Cc: Anshuman Khandual , linux-arm-kernel@lists.infradead.org, Will Deacon , Ryan Roberts , Mark Rutland , Oliver Upton , Jonathan Corbet , Eric Auger , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 0/7] arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9 In-Reply-To: References: <20241220072240.1003352-1-anshuman.khandual@arm.com> <20250102160402.GB3990035-robh@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: robh@kernel.org, catalin.marinas@arm.com, anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org, will@kernel.org, ryan.roberts@arm.com, mark.rutland@arm.com, oliver.upton@linux.dev, corbet@lwn.net, eric.auger@redhat.com, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 07 Jan 2025 12:13:40 +0000, Catalin Marinas wrote: > > On Thu, Jan 02, 2025 at 10:04:02AM -0600, Rob Herring wrote: > > On Fri, Dec 20, 2024 at 12:52:33PM +0530, Anshuman Khandual wrote: > > > This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9 > > > registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already > > > being used in the kernel. This is required to prevent their EL1 access trap > > > into EL2. > > > > > > PMZR_EL0 register trap control i.e HDFGWTR2_EL2.nPMZR_EL0 remains unchanged > > > for now as it does not get accessed in the kernel, and there is no plan for > > > its access from user space. > > > > > > I have taken the liberty to pick up all the review tags for patches related > > > to tools sysreg update from the KVM FGT2 V2 patch series posted earlier. > > > > > > https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/ > > > > > > Rob had earler mentioned about FEAT_FGT2 based trap control requirement for > > > FEAT_PMUv3p9 registers that are currently being used in kernel. The context > > > can be found here. > > > > > > https://lore.kernel.org/all/20241216234251.GA629562-robh@kernel.org/ > > > > > > This series is based on v6.13-rc3 > > > > > > Cc: Catalin Marinas > > > Cc: Will Deacon > > > Cc: Marc Zyngier > > > Cc: Ryan Roberts > > > Cc: Mark Rutland > > > Cc: Mark Brown > > > Cc: Rob Herring > > > Cc: Oliver Upton > > > Cc: Jonathan Corbet > > > Cc: Eric Auger > > > Cc: kvmarm@lists.linux.dev > > > Cc: linux-doc@vger.kernel.org > > > Cc: linux-kernel@vger.kernel.org > > > Cc: linux-arm-kernel@lists.infradead.org > > > > > > Anshuman Khandual (7): > > > arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1 > > > arm64/sysreg: Add register fields for HDFGRTR2_EL2 > > > arm64/sysreg: Add register fields for HDFGWTR2_EL2 > > > arm64/sysreg: Add register fields for HFGITR2_EL2 > > > arm64/sysreg: Add register fields for HFGRTR2_EL2 > > > arm64/sysreg: Add register fields for HFGWTR2_EL2 > > > arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9 > > > > In case it is not clear, this series should be applied to 6.13 as the 2 > > PMUv3p9 features already landed in 6.13 (per counter EL0 control) and > > 6.12 (ICNTR). > > So is this a fix that needs backporting to 6.12 or 6.13, e.g. fix for > d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction > counter")? It's pretty late in the cycle to take the series for 6.13. > > But does KVM actually expose the feature to EL1 in ID_AA64DFR1_EL1 and > than traps it at EL2? We limit the PMU emulation to v3p8, so *hopefully* this doesn't trip anything in KVM, even if we don't advertise support for these features. This has been tested, right? Thanks, M. -- Without deviation from the norm, progress is not possible.