From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AD722FFFA4; Wed, 22 Oct 2025 08:06:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761120363; cv=none; b=HM3aJJRIkG7eQcTciyo5QFbJ6FqxQAbrp9svVChqqIsqUtZOLKNN3cah0wczp4NYBCVuiaEx61bjD+wGqSn67ixCdXmh745XtyFzPCN84et8fAM/D5Y72nDOlQPgNVMAnKdbzKwaOhvJaqz3qTqtNrMTowAFQm2Jh5Qd1mkNeZs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761120363; c=relaxed/simple; bh=sEGPFxVuNAAvcbxq9cmERi5JemJMBcOvQ+wey3400IM=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=pZhEbrIrJvGQa9tYbrSbGyrG7OmYiX1xo57oMINicNOyDEbvHoBRAblXSpFK5R7tGYyL7QtReB9K2Vkneo7lcvik38KAYOaZGo1MeVseqCQ1howXn4k6HFQyyJiUh2szpQaLNshHCsdG4YLiuPcOYNGc5U7Of9WlxDiUIvKtLB8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kFfAo+E7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kFfAo+E7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 14654C4CEE7; Wed, 22 Oct 2025 08:06:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761120363; bh=sEGPFxVuNAAvcbxq9cmERi5JemJMBcOvQ+wey3400IM=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=kFfAo+E7F7mRth6Qp6bcZHzRhYDaHJ1asp5cb2jSUky6GXKe0h26lajT6YkeNahBh iXitqeoJRyGNUi+OA3B4bit9M/7fzpupAY++s7JK+zw4LXxY/APb3lHefJZ1s+SMnp VHdDht+/dvp/u1UtDeLPn03qXOBFiFyoU8zNxwCiHt2gQN6XT2oBqX6xOD+JTQ9kY8 igU7gVk1bf16OLvFepxZ3rIjn+PgMQUsQ7bvlHeGLfsk5tY+AYQ88RPaELTWDJdaWz nJvs17nvzrUjd6a6FRUv8JyFl34omRMviDlT8KrrF5cDW0WtncjJ1nOO2sq234EeQK tDHIsEttYFU0w== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vBTr6-0000000G6ap-1UvE; Wed, 22 Oct 2025 08:06:00 +0000 Date: Wed, 22 Oct 2025 09:05:59 +0100 Message-ID: <867bwnwec8.wl-maz@kernel.org> From: Marc Zyngier To: "Liao, Chang" Cc: , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH] arm64: Add kernel parameter to disable trap EL0 accesses to IMPDEF regs In-Reply-To: References: <20251021115428.557084-1-liaochang1@huawei.com> <86ecqwwig3.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: liaochang1@huawei.com, corbet@lwn.net, catalin.marinas@arm.com, will@kernel.org, akpm@linux-foundation.org, paulmck@kernel.org, pawan.kumar.gupta@linux.intel.com, mingo@kernel.org, bp@alien8.de, kees@kernel.org, arnd@arndb.de, fvdl@google.com, broonie@kernel.org, oliver.upton@linux.dev, yeoreum.yun@arm.com, james.morse@arm.com, ardb@kernel.org, hardevsinh.palaniya@siliconsignals.io, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Wed, 22 Oct 2025 02:35:02 +0100, "Liao, Chang" wrote: >=20 > =E5=9C=A8 2025/10/21 20:25, Marc Zyngier =E5=86=99=E9=81=93: > > On Tue, 21 Oct 2025 12:54:28 +0100, > > Liao Chang wrote: > >> > >> Add kernel parameter to allow system-wide EL0 access to IMPDEF system > >> regregisters and instructions without trapping to EL1/EL2. Since trap > >> overhead will compromises benefits, and it's even worse in > >> virtualization on CPU where certain IMPDEF registers and instructions > >> are designed for EL0 performance use. > >=20 > > Since you mention virtualisation, I want to be clear: there is no way > > I will consider anything like this for KVM. KVM will always trap and > > UNDEF such register accesses, no matter where they come from (EL0 or > > EL1). > >=20 > > Allowing such registers to be accessed from within a guest would make > > it impossible to context-switch or save/restore the guest correctly. >=20 > You've got that right, it seems like both the guest and the host would > need to save and restore those IMDDEF registers with the VM or task > context.The only exception would be if the registers aren't for saving > state or configuration, but instead just act as an interface to trigger > a special CPU function, such as ICC_IAR1. Funny that you mention the IAR register. Because contrary to what you seem to indicate, IAR does impact state outside of simply acknowledging an interrupt. What do you think happens to PMR, APRs, and so on? M. --=20 Without deviation from the norm, progress is not possible.