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Thu, 13 Mar 2025 18:36:12 +0000 Date: Thu, 13 Mar 2025 18:36:10 +0000 Message-ID: <86h63wok11.wl-maz@kernel.org> From: Marc Zyngier To: Ryan Roberts Cc: =?UTF-8?B?TWlrb8WCYWo=?= Lenczewski , suzuki.poulose@arm.com, yang@os.amperecomputing.com, corbet@lwn.net, catalin.marinas@arm.com, will@kernel.org, jean-philippe@linaro.org, robin.murphy@arm.com, joro@8bytes.org, akpm@linux-foundation.org, mark.rutland@arm.com, joey.gouly@arm.com, james.morse@arm.com, broonie@kernel.org, anshuman.khandual@arm.com, oliver.upton@linux.dev, ioworker0@gmail.com, baohua@kernel.org, david@redhat.com, jgg@ziepe.ca, shameerali.kolothum.thodi@huawei.com, nicolinc@nvidia.com, mshavit@google.com, jsnitsel@redhat.com, smostafa@google.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev Subject: Re: [PATCH v3 1/3] arm64: Add BBM Level 2 cpu feature In-Reply-To: References: <20250313104111.24196-2-miko.lenczewski@arm.com> <20250313104111.24196-3-miko.lenczewski@arm.com> <86ikocomvd.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: ryan.roberts@arm.com, miko.lenczewski@arm.com, suzuki.poulose@arm.com, yang@os.amperecomputing.com, corbet@lwn.net, catalin.marinas@arm.com, will@kernel.org, jean-philippe@linaro.org, robin.murphy@arm.com, joro@8bytes.org, akpm@linux-foundation.org, mark.rutland@arm.com, joey.gouly@arm.com, james.morse@arm.com, broonie@kernel.org, anshuman.khandual@arm.com, oliver.upton@linux.dev, ioworker0@gmail.com, baohua@kernel.org, david@redhat.com, jgg@ziepe.ca, shameerali.kolothum.thodi@huawei.com, nicolinc@nvidia.com, mshavit@google.com, jsnitsel@redhat.com, smostafa@google.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 13 Mar 2025 18:22:00 +0000, Ryan Roberts wrote: >=20 > On 13/03/2025 17:34, Marc Zyngier wrote: > > On Thu, 13 Mar 2025 10:41:10 +0000, > > Miko=C5=82aj Lenczewski wrote: > >> > >> diff --git a/arch/arm64/kernel/pi/idreg-override.c b/arch/arm64/kernel= /pi/idreg-override.c > >> index c6b185b885f7..9728faa10390 100644 > >> --- a/arch/arm64/kernel/pi/idreg-override.c > >> +++ b/arch/arm64/kernel/pi/idreg-override.c > >> @@ -209,6 +209,7 @@ static const struct ftr_set_desc sw_features __pre= l64_initconst =3D { > >> FIELD("nokaslr", ARM64_SW_FEATURE_OVERRIDE_NOKASLR, NULL), > >> FIELD("hvhe", ARM64_SW_FEATURE_OVERRIDE_HVHE, hvhe_filter), > >> FIELD("rodataoff", ARM64_SW_FEATURE_OVERRIDE_RODATA_OFF, NULL), > >> + FIELD("nobbml2", ARM64_SW_FEATURE_OVERRIDE_NOBBML2, NULL), > >> {} > >> }, > >> }; > >> @@ -246,6 +247,7 @@ static const struct { > >> { "rodata=3Doff", "arm64_sw.rodataoff=3D1" }, > >> { "arm64.nolva", "id_aa64mmfr2.varange=3D0" }, > >> { "arm64.no32bit_el0", "id_aa64pfr0.el0=3D1" }, > >> + { "arm64.nobbml2", "arm64_sw.nobbml2=3D1" }, > >=20 > > Why is that a SW feature? This looks very much like a HW feature to > > me, and you should instead mask out ID_AA64MMFR2_EL1.BBM, and be done > > with it. Something like: >=20 > I think this implies that we would expect the BBM field to be advertising= BBML2 > support normally and we would check for that as part of the cpufeature > detection. That's how Miko was doing it in v2, but Yang pointed out that > AmpereOne, which supports BBML2+NOABORT semantics, doesn't actually adver= tise > BBML2 in its MMFR2. So we don't want to check that field, and instead rely > solely on the MIDR allow-list + a command line override. It was me that > suggested putting that in the SW feature register, and I think that still= sounds > like the right solution for this situation? I think this is mixing two different things: - preventing BBM-L2 from being visible to the kernel: this is what my suggestion is doing by nuking an architectural feature in the relevant register - random HW not correctly advertising what they are doing: this is an erratum workaround I'd rather we don't conflate the two things, and make them very explicitly distinct. Thanks, M. --=20 Without deviation from the norm, progress is not possible.