From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8CD98595C; Tue, 2 Apr 2024 14:53:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712069617; cv=none; b=IQc5puMsMAKZO99uY5aqVJ+ExfzFV8QAetmlXBGMpR3bodV9UOrFNK1O0cR2i1MN+SlpTOyS2V5IPhVgeDvYUiVJtvw264Za+VnCN4oicacu+Cy9d9dobziRoEzjw6hE/piLuoNTdm2CBoiD34wCqb8aBwHDFl6zkoshzXU4s3Y= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712069617; c=relaxed/simple; bh=vhQsnvRHzwOy3ox3OvUmqvwn0itwQb57/FmYwbndCXU=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=tdhKOhAIJB09r6zXm66mKr7tPndtFmuX2mUgV6t7lsvvA4tCvhYdH6lpOcuCmWes+DYrUWhlY4sBxpm7LPCzWbFklpkx8DCfilIGIS5RzippkjiGbd20mDnpChP3MLrJpGaVbvJYaMtDbScXNrdE782nEfdejQanZYrIjwSGKwU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=u9wM5BM1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="u9wM5BM1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 509FAC43390; Tue, 2 Apr 2024 14:53:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712069616; bh=vhQsnvRHzwOy3ox3OvUmqvwn0itwQb57/FmYwbndCXU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=u9wM5BM1zVlflI8QFJDAHZYDZYOnPeNYUCR981yXBTjIUiYAuk/3ukwrzYyE9RB94 ggNYHgQ1aWLaJAIwPMuPzimCq9JWUddvfke5tuHoM0dsQKwtlwps5xe/l4EwBAzHDD rf1z2ocnPeEVj5O5c+AsMaSSwuS16ukcZIEKrjjEBxANfz4eCcf1IS4sLyBX7WGV4J X6bfAXGXEkMAukyHifrFowQ8fi42i71UHSa2nc5rdtHTyYs00rXjuHJJ55XSR2HdyJ 0d0USc13F8w/JmKNxjLr8RyCue8Q7EheKu9KzyehW7omtUJefOH2yADQqrus5BNuSp yCsACeDACsJbQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1rrfW1-000lX6-Ji; Tue, 02 Apr 2024 15:53:33 +0100 Date: Tue, 02 Apr 2024 15:53:33 +0100 Message-ID: <86h6gju87m.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: Catalin Marinas , Will Deacon , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave Martin , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v6 1/5] KVM: arm64: Share all userspace hardened thread data with the hypervisor In-Reply-To: References: <20240329-arm64-2023-dpisa-v6-0-ba42db6c27f3@kernel.org> <20240329-arm64-2023-dpisa-v6-1-ba42db6c27f3@kernel.org> <87msqesoty.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: broonie@kernel.org, catalin.marinas@arm.com, will@kernel.org, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, corbet@lwn.net, shuah@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave.Martin@arm.com, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 02 Apr 2024 15:34:27 +0100, Mark Brown wrote: > > [1 ] > On Sun, Mar 31, 2024 at 11:00:41AM +0100, Marc Zyngier wrote: > > Mark Brown wrote: > > > > As part of the lazy FPSIMD state transitioning done by the hypervisor we > > > currently share the userpsace FPSIMD state in thread->uw.fpsimd_state with > > > the host. Since this struct is non-extensible userspace ABI we have to keep > > > Using the same representation is just pure convenience, and nothing > > requires us to use the it in the kernel/hypervisor. > > Indeed, the additional data seemed contained enough that it was a > reasonable tradeoff. > > > > the definition as is but the addition of FPMR in the 2023 dpISA means that > > > we will want to share more storage with the host. To facilitate this > > > refactor the current code to share the entire thread->uw rather than just > > > the one field. > > > So this increase the required sharing with EL2 from 528 bytes to > > 560. Not a huge deal, but definitely moving in the wrong direction. Is > > there any plans to add more stuff to this structure that wouldn't be > > *directly* relevant to the hypervisor? > > I'm not aware of any current plans to extend this. > > > > @@ -640,7 +641,7 @@ struct kvm_vcpu_arch { > > > struct kvm_guest_debug_arch vcpu_debug_state; > > > struct kvm_guest_debug_arch external_debug_state; > > > > > > - struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */ > > > + struct thread_struct_uw *host_uw; /* hyp VA */ > > > struct task_struct *parent_task; > > > Well, this is going away, and you know it. > > Sure, those patches are still in flight though. It does seem reasonable > to target the current code. Sure, if your intent is for this code not to be merged. Because it means this series assumes a different data life cycle, and the review effort spent on it will be invalidated once you move to the per-CPU state. M. -- Without deviation from the norm, progress is not possible.