From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 118CA30ACF0; Mon, 8 Sep 2025 18:43:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757356981; cv=none; b=AVDHMZ2Lk7VP1T9oRmEGkOyHN9/SCFVwBnX5v+zaoyv5w6hMMxMtHRjHTkCptsFmn1e0jk4j/74V1xzyMhRIWLm7WBCB4SObaW9nGNjWsf9rxH15Q2dAC0Dwi1Cjqyy+cni3F58IrW+hxRM1tvMLm7PLKbpTdlmfrjuhWmVrX38= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757356981; c=relaxed/simple; bh=BZVL1wCaBWzQfdJch1ffdxC/Fe3h5D6JkG5PQqCRoEo=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=Y/37K/4pkojn3pJS3srA8pgiPO7U7qndxzxjqf5ZXC7NWUCzTKPPMR0fJxB9Nzfdf739cxeIEUZN448ykdMS62/gNWWoSl9cHbp8FI/eNpUJyOzQZg65G/v68hB+yAe0KrHFwQ4N8z4l3QPFoFEJT8/m9pGO4C0QLzu0fwwRKxA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pUD1sI4l; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pUD1sI4l" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 916A0C4CEF1; Mon, 8 Sep 2025 18:43:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757356980; bh=BZVL1wCaBWzQfdJch1ffdxC/Fe3h5D6JkG5PQqCRoEo=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=pUD1sI4lf9yVrcmuXxRcHKSwejJd8c7Pz3F4LcIN1L9q01ptztyLhz0L876ijAl4k vLhuoYjLukD+8FvAXwldQ1+Jo79G0dCTa6AU6rlHs7nyEOe6rE1ChxoMg2MmdeDa1w rFvN5+FkH/YQxm3hsZpOi6P1mDItF/kkMLvbUhwN4vr5C+cLhA8sTHEeVKGXuVO9ut cbEHg1ZKXV9h2nIJDiYoMltuktdMftCOroIsdwE+4BnCCKwubAlFDCt0p+ncfvbH34 gU97IYcsuJFW9hr4TlVYhYHOi6Us93CwBsQ5F2Wowxf+0nPdBJvD3wmnC1l0W93GnS Vmr9kye74yOwA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1uvgpO-00000004QJ8-15nD; Mon, 08 Sep 2025 18:42:58 +0000 Date: Mon, 08 Sep 2025 19:42:57 +0100 Message-ID: <86segwdbv2.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: Catalin Marinas , Will Deacon , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v15 4/6] KVM: arm64: Set PSTATE.EXLOCK when entering an exception In-Reply-To: References: <20250820-arm64-gcs-v15-0-5e334da18b84@kernel.org> <20250820-arm64-gcs-v15-4-5e334da18b84@kernel.org> <87ms7tk5y4.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: broonie@kernel.org, catalin.marinas@arm.com, will@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, shuah@kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 21 Aug 2025 21:44:21 +0100, Mark Brown wrote: > > On Wed, Aug 20, 2025 at 11:02:11PM +0100, Marc Zyngier wrote: > > Mark Brown wrote: > > > > + // EL, or to GCSCR_ELx.EXLOCKEN for an exception to the same > > > + // exception level. See ARM DDI 0487 RWTXBY, D.1.3.2 in K.a. nit: I think you can drop the section number in the ARM ARM. The rule "numbers" are stable across revision of the document, and K.a is already absolutely ancient (over a year old and two revisions behind). > > > + new |= enter_exception64_gcs(vcpu, mode, target_mode); > > > + > > > new |= PSR_D_BIT; > > > new |= PSR_A_BIT; > > > new |= PSR_I_BIT; > > > But that's not the only case where we have to deal with EXLOCK, is it? > > What of ERET and its PAuth variants? R_TYTWB says: > > > > > If in AArch64 state, any of the following situations can cause an > > illegal exception return: > > > > [...] > > > > - If the Effective value of GCSCR_ELx.EXLOCKEN is 1 and PSTATE.EXLOCK > > is 0, the execution of an exception return instruction to return to > > the current Exception level ELx. > > > > > My reading of the spec is that this needs handling. > > Am I right in thinking that this handling is needed for the NV case > only? So far, NV is indeed the only case where we have to emulate ERET. M. -- Without deviation from the norm, progress is not possible.