From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DA2835977; Sat, 22 Nov 2025 12:54:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763816058; cv=none; b=RrTkQeMHk+sOtew16JZofxf/hzbAD1dKzrcCc9AxR4IL9EPYVxa+arnJz9ibLftsmo3g+02z75tlKNJ/+dRutTAgVPF8ho5J/5WWwkvLbRjVgkBo30ZMGPEc3EP22ys7c4ygDSl8s/B+DD82Df2IsApXsUnfhFwKOXx2jPtzT38= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763816058; c=relaxed/simple; bh=FR4E8hZalGj/6XCc4oY1XezvA/TPT41+qYdS/PdvxL4=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=j9ubjXcgjqZ8EhwcGj6uVKoBF5eA0vIOX9pAaYah8V2dQ3hBDX4tJ7/d+5aINk9bRqQoy5i1XQRkfVyOQSLY5YmrM+ZigRHohQFBpqGxWTKL+xqJ1zZD4NG6u+dw+D1ke3+XKQK+1n//pqR/8O1/wg7B3nRfJdDs7fNMCrA8DDc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=teQPP7OG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="teQPP7OG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 23D9CC4CEF5; Sat, 22 Nov 2025 12:54:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763816058; bh=FR4E8hZalGj/6XCc4oY1XezvA/TPT41+qYdS/PdvxL4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=teQPP7OGmS7K1rnsd+7oofZyDlXrWbuIbE4+cZB9/w4V9zBc1VH+Oumfx2SmSWfp9 39TNXqP63o80SY2qBQlGRl5XT6W2CgMB0wWBoF3bgsRpCcO0Knj3eYS/d1dy4kFfY/ EtC1YncnkpY1uzqYMnfxq7Xw7DEeRRMriFbRmvsEv/ERVTFIxpJMHUcQyFvqgbPU0J h8TPfAmOUPmg8Qij57brvYEgWmVv6HosWEBwOu/qaYdhDGwMvUdk0mm8j2sfM+M/yM v5GUxus2/M7WJGaEWKCZbI4RdBxRfymBuGBWCBnu5oBdskAkttF2ExQDC7fiRiB3sA O/ymaH+heZlOw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vMn84-00000007USt-0CFe; Sat, 22 Nov 2025 12:54:16 +0000 Date: Sat, 22 Nov 2025 12:54:15 +0000 Message-ID: <86v7j2qlc8.wl-maz@kernel.org> From: Marc Zyngier To: Tian Zheng Cc: , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v2 2/5] KVM: arm64: Support set the DBM attr during memory abort In-Reply-To: <20251121092342.3393318-3-zhengtian10@huawei.com> References: <20251121092342.3393318-1-zhengtian10@huawei.com> <20251121092342.3393318-3-zhengtian10@huawei.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: zhengtian10@huawei.com, oliver.upton@linux.dev, catalin.marinas@arm.com, corbet@lwn.net, pbonzini@redhat.com, will@kernel.org, linux-kernel@vger.kernel.org, yuzenghui@huawei.com, wangzhou1@hisilicon.com, yezhenyu2@huawei.com, xiexiangyou@huawei.com, zhengchuan@huawei.com, linuxarm@huawei.com, joey.gouly@arm.com, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, suzuki.poulose@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 21 Nov 2025 09:23:39 +0000, Tian Zheng wrote: > > From: eillon > > Add DBM support to automatically promote write-clean pages to > write-dirty, preventing users from being trapped in EL2 due to > missing write permissions. > > Since the DBM attribute was introduced in ARMv8.1 and remains > optional in later architecture revisions, including ARMv9.5. What is the relevance of this statement? > > Support set the DBM attr during user_mem_abort(). I don't think this commit message accurately describes what the code does. This merely adds support to the page table code to set the DBM bit in the S2 PTE, and nothing else. M. -- Without deviation from the norm, progress is not possible.