From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AE06207A3A; Sat, 22 Nov 2025 12:40:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763815230; cv=none; b=E98CogdVFqeiUS2dJvaDcdJtfIlEGvwlkHe47Wr7ObMJPY4aIBSCzRMmrpiMmCQzD/kcVseP6CXF1wXVlQ1ay6esd5vX7HSRmXnZvsjQiBi8UgOE83QZr4u4NSpQeLYaZE0/qKMacuWxc1r8bMuqaL9WTXMRoun0Y0CEuMoJBN4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763815230; c=relaxed/simple; bh=BdnKYTAKaORHGO2Q/Ihj95imsb6E3FqedhQAygwOtME=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=NvCAX4SuBlYbjU+KsyxMpI20wIl3hwr50amYeTFJEQnQAbFVfs8D57+ZOUavp3sd+/KnWHm/skdiZ8cYKyKoKbvwvsv1HrWLvmiHGfQCceD88aoj2z0JblGAFKp1bHt1tUGffymrXCj6XSesFGr3KO2Lsw/fSGcJJLZCLuo9Jpw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=agJf8a7L; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="agJf8a7L" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1386EC4CEF5; Sat, 22 Nov 2025 12:40:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763815230; bh=BdnKYTAKaORHGO2Q/Ihj95imsb6E3FqedhQAygwOtME=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=agJf8a7LyH/iIOyJQTWgVeUmnxNhDQOOQVYulw37B5bbbtdEDM/eyEMHAwCPpEmr2 BNi/CTDYPjU8zu768mBfk8h3mncoDFkUX0vbxoflPmFj+DKw2Yaq1tWYyDktArgl3V 8UL7Dl+nMSEnpTHVtgjNWsbXP7huorjOVkZLn8GU3ywsIewGcdpGF5gzwsloFdrQCV 3JTm3wiV7cPAP+SHF+5abJijTyW1SVbvYuCvWyuLo+fsUIwDCJZGVeJKPK/R2jgEy5 Qm1qe8852o3PGDa7xmR+LRQn13R/rezvVHJDZ2BOG5+kPAOAvV0nVwBbqDQySQb3aL tlkjsqwx00p9Q== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vMmuh-00000007U9L-2jRe; Sat, 22 Nov 2025 12:40:27 +0000 Date: Sat, 22 Nov 2025 12:40:27 +0000 Message-ID: <86wm3iqlz8.wl-maz@kernel.org> From: Marc Zyngier To: Tian Zheng Cc: , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v2 1/5] arm64/sysreg: Add HDBSS related register information In-Reply-To: <20251121092342.3393318-2-zhengtian10@huawei.com> References: <20251121092342.3393318-1-zhengtian10@huawei.com> <20251121092342.3393318-2-zhengtian10@huawei.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: zhengtian10@huawei.com, oliver.upton@linux.dev, catalin.marinas@arm.com, corbet@lwn.net, pbonzini@redhat.com, will@kernel.org, linux-kernel@vger.kernel.org, yuzenghui@huawei.com, wangzhou1@hisilicon.com, yezhenyu2@huawei.com, xiexiangyou@huawei.com, zhengchuan@huawei.com, linuxarm@huawei.com, joey.gouly@arm.com, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, suzuki.poulose@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 21 Nov 2025 09:23:38 +0000, Tian Zheng wrote: > > From: eillon > > The ARM architecture added the HDBSS feature and descriptions of > related registers (HDBSSBR/HDBSSPROD) in the DDI0601(ID121123) version, > add them to Linux. > > Signed-off-by: eillon > Signed-off-by: Tian Zheng > --- > arch/arm64/include/asm/esr.h | 2 ++ > arch/arm64/include/asm/kvm_arm.h | 1 + > arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++ > 3 files changed, 31 insertions(+) > > diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h > index e1deed824464..a6f3cf0b9b86 100644 > --- a/arch/arm64/include/asm/esr.h > +++ b/arch/arm64/include/asm/esr.h > @@ -159,6 +159,8 @@ > #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) > > /* ISS2 field definitions for Data Aborts */ > +#define ESR_ELx_HDBSSF_SHIFT (11) > +#define ESR_ELx_HDBSSF (UL(1) << ESR_ELx_HDBSSF_SHIFT) > #define ESR_ELx_TnD_SHIFT (10) > #define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT) > #define ESR_ELx_TagAccess_SHIFT (9) > diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h > index 1da290aeedce..b71122680a03 100644 > --- a/arch/arm64/include/asm/kvm_arm.h > +++ b/arch/arm64/include/asm/kvm_arm.h > @@ -124,6 +124,7 @@ > TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK) > > /* VTCR_EL2 Registers bits */ > +#define VTCR_EL2_HDBSS (1UL << 45) I think it is time to convert VTCR_EL2 to the sysreg infrastructure instead of adding extra bits here. M. -- Without deviation from the norm, progress is not possible.