Re: [PATCH V5 1/5] PCI: Add TLP Processing Hints (TPH) support

[Wei Huang <wei.huang2@amd.com>]

On 9/23/24 7:07 AM, Alejandro Lucero Palau wrote:
> 

...

>> +/**
>> + * pcie_enable_tph - Enable TPH support for device using a specific ST mode
>> + * @pdev: PCI device
>> + * @mode: ST mode to enable. Current supported modes include:
>> + *
>> + *   - PCI_TPH_ST_NS_MODE: NO ST Mode
>> + *   - PCI_TPH_ST_IV_MODE: Interrupt Vector Mode
>> + *   - PCI_TPH_ST_DS_MODE: Device Specific Mode
>> + *
>> + * Checks whether the mode is actually supported by the device before enabling
>> + * and returns an error if not. Additionally determines what types of requests,
>> + * TPH or extended TPH, can be issued by the device based on its TPH requester
>> + * capability and the Root Port's completer capability.
>> + *
>> + * Return: 0 on success, otherwise negative value (-errno)
>> + */
>> +int pcie_enable_tph(struct pci_dev *pdev, int mode)
>> +{
>> +	u32 reg;
>> +	u8 dev_modes;
>> +	u8 rp_req_type;
>> +
>> +	/* Honor "notph" kernel parameter */
>> +	if (pci_tph_disabled)
>> +		return -EINVAL;
>> +
>> +	if (!pdev->tph_cap)
>> +		return -EINVAL;
>> +
>> +	if (pdev->tph_enabled)
>> +		return -EBUSY;
>> +
>> +	/* Sanitize and check ST mode comptability */
>> +	mode &= PCI_TPH_CTRL_MODE_SEL_MASK;
>> +	dev_modes = get_st_modes(pdev);
>> +	if (!((1 << mode) & dev_modes))
> 
> 
> This is wrong. The mode definition is about the bit on and not about bit
> position. You got this right in v4 ...

This code is correct. In V5, I changed the "mode" parameter to the 
following values, as defined in TPH Ctrl register. These values are 
defined as bit positions:

PCI_TPH_ST_NS_MODE: NO ST Mode
PCI_TPH_ST_IV_MODE: Interrupt Vector Mode
PCI_TPH_ST_DS_MODE: Device Specific Mode

In V4, "mode" is defined as masks of TPH Cap register. I felt that V5 
looks more straightforward:

V4: pcie_enable_tph(dev, PCI_TPH_CAP_ST_IV)
vs.
V5: pcie_enable_tph(dev, PCI_TPH_ST_IV_MODE)

> 
> 
>> +		return -EINVAL;