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b=yfrBmF6n9B3/9oSRgFpqKVWAD+dj8gD4NEse5R5q2bV/PKkF72KULAZJIIgsG0QXJM9fgToG3NpECFUtaT2fjX2AHc3yassw9/k7QItshGnQiee0b3E/zqGOK0A7Ik2/vHb1VtkPb+KHNL2O0r/obaCC/Lu5xtY/yl4Vo2hTri0= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from DM6PR12MB4877.namprd12.prod.outlook.com (2603:10b6:5:1bb::24) by DS0PR12MB6630.namprd12.prod.outlook.com (2603:10b6:8:d2::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7982.25; Mon, 23 Sep 2024 20:27:29 +0000 Received: from DM6PR12MB4877.namprd12.prod.outlook.com ([fe80::92ad:22ff:bff2:d475]) by DM6PR12MB4877.namprd12.prod.outlook.com ([fe80::92ad:22ff:bff2:d475%3]) with mapi id 15.20.7982.022; Mon, 23 Sep 2024 20:27:29 +0000 Message-ID: <87111ebf-9cfd-4e14-9c03-05aa65330070@amd.com> Date: Mon, 23 Sep 2024 15:27:25 -0500 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V5 1/5] PCI: Add TLP Processing Hints (TPH) support To: Alejandro Lucero Palau , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, netdev@vger.kernel.org Cc: Jonathan.Cameron@Huawei.com, helgaas@kernel.org, corbet@lwn.net, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, alex.williamson@redhat.com, gospo@broadcom.com, michael.chan@broadcom.com, ajit.khaparde@broadcom.com, somnath.kotur@broadcom.com, andrew.gospodarek@broadcom.com, manoj.panicker2@amd.com, Eric.VanTassell@amd.com, vadim.fedorenko@linux.dev, horms@kernel.org, bagasdotme@gmail.com, bhelgaas@google.com, lukas@wunner.de, paul.e.luse@intel.com, jing2.liu@intel.com References: <20240916205103.3882081-1-wei.huang2@amd.com> <20240916205103.3882081-2-wei.huang2@amd.com> From: Wei Huang Content-Language: en-US In-Reply-To: Content-Type: text/plain; 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Current supported modes include: >> + * >> + * - PCI_TPH_ST_NS_MODE: NO ST Mode >> + * - PCI_TPH_ST_IV_MODE: Interrupt Vector Mode >> + * - PCI_TPH_ST_DS_MODE: Device Specific Mode >> + * >> + * Checks whether the mode is actually supported by the device before enabling >> + * and returns an error if not. Additionally determines what types of requests, >> + * TPH or extended TPH, can be issued by the device based on its TPH requester >> + * capability and the Root Port's completer capability. >> + * >> + * Return: 0 on success, otherwise negative value (-errno) >> + */ >> +int pcie_enable_tph(struct pci_dev *pdev, int mode) >> +{ >> + u32 reg; >> + u8 dev_modes; >> + u8 rp_req_type; >> + >> + /* Honor "notph" kernel parameter */ >> + if (pci_tph_disabled) >> + return -EINVAL; >> + >> + if (!pdev->tph_cap) >> + return -EINVAL; >> + >> + if (pdev->tph_enabled) >> + return -EBUSY; >> + >> + /* Sanitize and check ST mode comptability */ >> + mode &= PCI_TPH_CTRL_MODE_SEL_MASK; >> + dev_modes = get_st_modes(pdev); >> + if (!((1 << mode) & dev_modes)) > > > This is wrong. The mode definition is about the bit on and not about bit > position. You got this right in v4 ... This code is correct. In V5, I changed the "mode" parameter to the following values, as defined in TPH Ctrl register. These values are defined as bit positions: PCI_TPH_ST_NS_MODE: NO ST Mode PCI_TPH_ST_IV_MODE: Interrupt Vector Mode PCI_TPH_ST_DS_MODE: Device Specific Mode In V4, "mode" is defined as masks of TPH Cap register. I felt that V5 looks more straightforward: V4: pcie_enable_tph(dev, PCI_TPH_CAP_ST_IV) vs. V5: pcie_enable_tph(dev, PCI_TPH_ST_IV_MODE) > > >> + return -EINVAL;