[PATCH v2] Documentation: Fix minor typos

[PATCH v2] Documentation: Fix minor typos

[Ranganath V N]

Corrected a few spelling errors and improved the phrasing
changes since v1:
--corrected as per review

Signed-off-by: Ranganath V N <vnranganath.20@gmail.com>
---
 Documentation/arch/loongarch/irq-chip-model.rst | 4 ++--
 Documentation/arch/x86/cpuinfo.rst              | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/Documentation/arch/loongarch/irq-chip-model.rst b/Documentation/arch/loongarch/irq-chip-model.rst
index a7ecce11e445..8f5c3345109e 100644
--- a/Documentation/arch/loongarch/irq-chip-model.rst
+++ b/Documentation/arch/loongarch/irq-chip-model.rst
@@ -139,13 +139,13 @@ Feature EXTIOI_HAS_INT_ENCODE is part of standard EIOINTC. If it is 1, it
 indicates that CPU Interrupt Pin selection can be normal method rather than
 bitmap method, so interrupt can be routed to IP0 - IP15.
 
-Feature EXTIOI_HAS_CPU_ENCODE is entension of V-EIOINTC. If it is 1, it
+Feature EXTIOI_HAS_CPU_ENCODE is extension of V-EIOINTC. If it is 1, it
 indicates that CPU selection can be normal method rather than bitmap method,
 so interrupt can be routed to CPU0 - CPU255.
 
 EXTIOI_VIRT_CONFIG
 ------------------
-This register is read-write register, for compatibility intterupt routed uses
+This register is read-write register, for compatibility interrupt routed uses
 the default method which is the same with standard EIOINTC. If the bit is set
 with 1, it indicated HW to use normal method rather than bitmap method.
 
diff --git a/Documentation/arch/x86/cpuinfo.rst b/Documentation/arch/x86/cpuinfo.rst
index dd8b7806944e..9f2e47c4b1c8 100644
--- a/Documentation/arch/x86/cpuinfo.rst
+++ b/Documentation/arch/x86/cpuinfo.rst
@@ -11,7 +11,7 @@ The list of feature flags in /proc/cpuinfo is not complete and
 represents an ill-fated attempt from long time ago to put feature flags
 in an easy to find place for userspace.
 
-However, the amount of feature flags is growing by the CPU generation,
+However, the number of feature flags is growing with each CPU generation,
 leading to unparseable and unwieldy /proc/cpuinfo.
 
 What is more, those feature flags do not even need to be in that file
-- 
2.43.0

Re: [PATCH v2] Documentation: Fix minor typos

[Randy Dunlap]

On 7/25/25 11:36 PM, Ranganath V N wrote:
> Corrected a few spelling errors and improved the phrasing
> changes since v1:
> --corrected as per review
> 
> Signed-off-by: Ranganath V N <vnranganath.20@gmail.com>

Reviewed-by: Randy Dunlap <rdunlap@infradead.org>

Thanks.

> ---
>  Documentation/arch/loongarch/irq-chip-model.rst | 4 ++--
>  Documentation/arch/x86/cpuinfo.rst              | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/arch/loongarch/irq-chip-model.rst b/Documentation/arch/loongarch/irq-chip-model.rst
> index a7ecce11e445..8f5c3345109e 100644
> --- a/Documentation/arch/loongarch/irq-chip-model.rst
> +++ b/Documentation/arch/loongarch/irq-chip-model.rst
> @@ -139,13 +139,13 @@ Feature EXTIOI_HAS_INT_ENCODE is part of standard EIOINTC. If it is 1, it
>  indicates that CPU Interrupt Pin selection can be normal method rather than
>  bitmap method, so interrupt can be routed to IP0 - IP15.
>  
> -Feature EXTIOI_HAS_CPU_ENCODE is entension of V-EIOINTC. If it is 1, it
> +Feature EXTIOI_HAS_CPU_ENCODE is extension of V-EIOINTC. If it is 1, it
>  indicates that CPU selection can be normal method rather than bitmap method,
>  so interrupt can be routed to CPU0 - CPU255.
>  
>  EXTIOI_VIRT_CONFIG
>  ------------------
> -This register is read-write register, for compatibility intterupt routed uses
> +This register is read-write register, for compatibility interrupt routed uses
>  the default method which is the same with standard EIOINTC. If the bit is set
>  with 1, it indicated HW to use normal method rather than bitmap method.
>  
> diff --git a/Documentation/arch/x86/cpuinfo.rst b/Documentation/arch/x86/cpuinfo.rst
> index dd8b7806944e..9f2e47c4b1c8 100644
> --- a/Documentation/arch/x86/cpuinfo.rst
> +++ b/Documentation/arch/x86/cpuinfo.rst
> @@ -11,7 +11,7 @@ The list of feature flags in /proc/cpuinfo is not complete and
>  represents an ill-fated attempt from long time ago to put feature flags
>  in an easy to find place for userspace.
>  
> -However, the amount of feature flags is growing by the CPU generation,
> +However, the number of feature flags is growing with each CPU generation,
>  leading to unparseable and unwieldy /proc/cpuinfo.
>  
>  What is more, those feature flags do not even need to be in that file

-- 
~Randy

Re: [PATCH v2] Documentation: Fix minor typos

[Jonathan Corbet]

Ranganath V N <vnranganath.20@gmail.com> writes:

> Corrected a few spelling errors and improved the phrasing
> changes since v1:
> --corrected as per review
>
> Signed-off-by: Ranganath V N <vnranganath.20@gmail.com>
> ---
>  Documentation/arch/loongarch/irq-chip-model.rst | 4 ++--
>  Documentation/arch/x86/cpuinfo.rst              | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)

Applied, thanks.

jon